Call for Papers

The Computer Science laboratory LIP6 of UPMC (University Pierre and Marie Curie), DIGITEO DIM and the Ile de France region are offering a post-doctoral position.

Location : LIP6, 104 av du Président Kennedy 75016, Paris, France.

LIP6 website: <http://www.lip6.fr <http://www.limsi.fr/index.en.html>>

Requirements for a candidate

============================

* A PhD in Computer Science or operations research;

* Expertise in at least one of the following fields : Scheduling, load balancing, approximation algorithms.

Offered

=======

* A full time, temporary appointment for a period of 1 year;

* Starting date: october 2009;

* Monthly salary: about 2000 Euros .

Framework: ORCYMELAN Project

========================

LIP6 and PRISM jointly lead ORCYMELAN, a project aimed at investigating scheduling problems issued from the code generation for loops on VLIW architectures, taking into account new constraints induced by register pressure and pipelined functional units.

This project is supported and funded by both the Région Île-de-France and the Digiteo Research Park (see <http://www.digiteo.fr/>).

Subject

======

The aim of the ORCYMELAN project is to provide efficient scheduling algorithms in terms of computation time as well as competitive ratio for an optimization criteria, that would map programs on VLIW architectures, taking into account register pressure and pipelined functional units.

Such a problem is usually decomposed in two parts. First, solving a scheduling problem without register pressure, and then a register allocation problem, leading sometimes to unfeasible solutions.

However, the PRISM team has developed and successfully experimented an approach which first consider register pressure and introduces new precedence constraints in the scheduling problem.

This approach may lead to a kind of constraints which has not been very much investigated until now: negative latencies.

If i and j are two jobs, and if we denote by s(i) the starting time of i, a negative latency constraint between i and j can be expressed as follows:

s(i)+l(i,j)<=s(j), with l(i,j)<=0

Such a constraint can be seen as a relative due-date between i and j: i must start at most -l(i,j) (positive) time units after j starts.

Notice that such constraints can be easily handled by graph algorithms if no resource constraints are considered. But even for simple resources like parallel processors, these constraints may lead to infeasibility, and require much attention to design good algorithms.

The postdoc candidate will take part in the study the theoretical scheduling problems arising from a precedence graph G with positive and negative latencies, and various resource constraints (parallel processors, typed processors, unitary RCPSP). Complexity results, as well as performance analysis of approximation algorithms, and experiments results are expected.

This study will take advantage of previous work in the field of approximation algorithms for scheduling problems with ordinary precedence constraints, and fixed due-dates. It should lead to both international journal publications and conferences with the members of the project.

Participating Teams and members

===============================

* Claire Hanen from Operations research team at LIP6, UPMC

* Sid Touati, Karine Deschinkel from PRISM, UVSQ

Application details

===================

* Dates: please apply as soon as possible.

* Please send:

- a CV (including publication list);

- links to PhD thesis and/or selected papers;

- a motivation letter presenting topics of interest.

to: Claire Hanen (claire.hanen@lip6.fr)

IBM Research @ The Watson Research Center in NY Post-Doctoral Position Job Description

The Dynamic Optimizations Group at IBM Research (Watson) is seeking a motivated post-doc to join the Liquid Metal project (http://www.research.ibm.com/liquidmetal). The goal of the Liquid Metal project is to allow hybrid and heterogeneous systems to be programmed in a single high-level and Object Oriented language that maps well to both CPUs and FPGAs (and everything in between). The project is interdisciplinary, spanning language design and implementation, compilation technology, high-level synthesis, and architecture virtualization.

We are looking for candidates with hands-on experience using FPGAs and with a strong background in computer architecture. A background in streaming, dataflow, or hardware description languages and related compilation technology is also essential.

Applications are expected to possess a doctorate degree in Computer Science or Electrical Engineering, and have demonstrated an ability to develop and execute a research plan, and have in-depth knowledge of current technologies and a command of research literature. We are seeking candidates with strong experience in programming and working with large software systems, who can work independently and in teams, and have excellent written and verbal communication skills.

Interested candidates should email Rodric Rabbah (rabbah@us.ibm.com) or David Bacon (dfb@watson.ibm.com). IBM is an equal opportunity employer.

POST-DOCTORAL POSITION

Paralelization of Optimization Algorithms for Finite Element Meshes

The SIANI research institute is seeking one candidate for a post-doctoral position at the University of Las Palmas de Gran Canaria (www.english.ulpgc.es), Las Palmas de Gran Canaria, Canary Islands, Spain.

The position will be part of the project financed by the Spanish government: Predictive Numerical Models for Environmental Management.

For more information, see the following link:

http://www.dca.iusiani.ulpgc.es/proyecto2008-2011/html_ingles/index.html.

The salary will be 1516 Euros/month during 12 months. More details about the official announcement of the post-doctoral position can be obtained from http://www.gobiernodecanarias.org/boc/2009/100/006.html (in Spanish).

The goal is to develop, model, implement and evaluate parallel programs for numerical algorithms that have been developed at the SIANI research institute (www.siani.es). These algorithms are used for generating optimal 2-D and 3-D meshes for finite element applications.

The candidates should have experience in parallel programming of mathematic applications, and experience in performance evaluation of parallel programs. Additionally, her or his Ph.D. must be valid in Spain. The candidates can send a summary of his/her curriculum vitae to Rafael Montenegro (rafa@dma.ulpgc.es) or Domingo Benitez (dbenitez@dis.ulpgc.es).

Deadline for applications: June 8th, 2009

PhD position in Networks-on-Chip research

The Parallel Architecture Group (GAP) at Technical University of Valencia (UPV), Spain, invites applications for funded research positions for PhD students in the area of networks-on-chip (NoCs). The position will be linked to the COMCAS (COmunication-centric MultiCore

ArchitectureS) research project, carried out with leading semiconductor European companies. The time frame for COMCAS is 2009-2012.

Candidates who are knowledgeable about interconnection networks and interested (not mandatory) in the following areas are encouraged to apply:

• Coding and compressing mechanisms for power-efficient communication in NoCs • Topology and Routing exploration in Multicore SoCs • Simulation expertise in application-based execution models (GEMS, SIMICS)

Applicants must hold a master or equivalent degree in computer engineering. Language skills: English

Salaries will be around 18200 euros per year (including taxes).

The GAP group is a research group with more than 30 researchers (including PhD and professors) focused mainly in high-performance networks for parallel systems (off-chip and on-chip). The GAP group also has strong links with other Universities in Spain that research in related topics, forming the ACCA group (http://www.acca-group.info/) with more than 130 people involved.

Applications can be submitted (preferably by email) until June 19.

Please direct questions and your application (your CV) to:

Prof. Dr. José Flich

Departamento DISCA

Escuela Técnica Superior de Ingeniería Informática Universidad Politécnica de Valencia 46020 Valencia Spain

Tel: +34 963877007, ext 75753

Fax: +34 963877579

Email: jflich@disca.upv.es

——————-

Some touristic info about Valencia:

The City of Valencia is located by the Mediterranean Sea in Spain.

Valencia is the third largest city in Spain and a major industrial center with a European Congress Center for international business and trade fairs. Valencia is full of history and culture and has a population of more than 900.000 people. Just strolling around the center of this buzzing city makes you feel good. One of the major attractions of Valencia is the historic old quarter which is full of gothic, baroque and modernist monuments and some excellent museums and art galleries.

Nevertheless, Valencia is a very modern city, with many recent buildings and entertainment centres. Probably, the most famous one is Ciudad de las Artes y de las Ciencias (City of Arts and Sciences) which was created by the local architect Santiago Calatrava. Valencia also has a new Formula 1 street circuit. There are also some great places to shop in Valencia.

Valencia is famous as the birthplace of paella. The bars and restaurants of this magical city offer mouth-watering cuisine. Transport is affordable, clean and enjoyable so it’s easy to get to the beach, harbour and other nice places in the city.

——————

A PhD research fellowship is offered in the Department of Computer and Information Science (IDI), Faculty of Information Technology, Mathematics and Electrical Engineering (IME) at the Norwegian University of Science and Technology (NTNU).

Multicore architectures and their associated software give many new opportunities to reduce the energy consumption of computers. Heat generation/power dissipation necessitates expensive cooling systems and is a serious and increasing problem in most IT systems. Furthermore, reduced energy consumption in IT equipment is a goal in all market segments (i.e. from sensor networks, via mobile phones, laptops, servers and up to compute clusters and supercomputers). Common for all these platforms is the widespread and increasing use of multicore technology. These new multicore solutions must balance the desire for low energy consumption against the need for high performance. Consequently, they are at the heart of the collective endeavor named “Green IT”.

In this research project, we will study the trade-off between low energy consumption and high performance. A crucial choice is the degree of parallelization, e.g. the distribution of the computations on one, a few or many processor-cores. The project includes evaluation of existing methods, techniques and tools for optimizing the metric performance/watt, as well as proposing and exploring new programming methods. System level simulations of both architecture and software will be used to evaluate the proposed techniques. Modern approaches such as design space exploration, autotuning and use of performance & energy counters is relevant. The research will be related to the activities in the research cluster “Programming model and OS” of EU-7FP HiPEAC2 NoE (Network of Excellence).

Further information on the fellowship may be obtained from Professor Lasse Natvig, mob. +47 906 44 580, e-mail lasse@idi.ntnu.no See also http://research.idi.ntnu.no/multicore/

Applications should be submitted to the Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, NO-7491 Trondheim, Norway, or by e-mail to application@ime.ntnu.no Applications should be marked IME-039-2009 Closing date: 2009-06-10

For further information, see this link:

http://innsida.ntnu.no/getfile.php/vedlegg/4a13a267bb3fe8.82866996/Ime-039-2009+Fulltxt.eng.pdf

One Ph.D position and one Post-doctoral position are available in run-time reconfigurable systems for Field Programmable Gate Arrays (FPGA) at University of Oslo, Norway.

Deadline for applications: May 29th, 2009

The positions are a part of the project "Context Switching Reconfigurable Hardware for Communication Systems", financed by the Norwegian Research Council.

The project consists of applying reconfigurable logic technology (FPGA) for new design and configuration schemes to implement run-time reconfigurable hardware systems. The goal is to develop, model and implement such systems for selected communication technology applications. The position will be located at the Robotics and Intelligent Systems research group http://www.ifi.uio.no/robin , Department of Informatics, University of Oslo, Norway. The project consists of a number of national and international collaborating partners and visits to these are planned for both positions.

The candidates should have a background from digital hardware design with research ambitions in reconfigurable logic technology. Thus, experience with FPGA design is necessary. Further, knowledge in communication technology including network technology is beneficial. Good skills in oral and written English are also required.

Salary (per year):

NOK 353 000 – 391 500 (PhD)

NOK 435 500 – 496 100 (Post-doc)

(depending on qualifications)

For more information including how to apply, see the full announcement here:

http://www.admin.uio.no/opa/ledige-stillinger/2009/vitenskapelige/PhDresearc

hFellowshipandFellowInformatics-2009-7219og7232.html

You may also contact me at jimtoer@ifi.uio.no for more information.

Open PhD position:
———————————————————————-
Parallelization, modeling and mapping of multiple adaptive streaming
applications on Multi-processor Systems-on-Chip (MPSoC)
———————————————————————-

Job Description:
———————————————————————-
The PhD student will research and develop novel methods, techniques,
and tools for modeling and parallelization of adaptive streaming
applications. The underling model of computation that will be used is
the Kahn Process Networks (KPN). Theoretical studies will be performed
to develop a modeling framework for multiple adaptive streaming
applications to be executed simultaneously onto a single heterogeneous
MPSoC. This research activity will include extension of the KPN model
to a model called Parameterized KPN where the dynamic/adaptive
behavior of streaming applications will be expressed at design time by
parameters. The exact values of these parameters have to be set at run
time depending on changes in the environment. The modeling framework
will be supported by the development of tools for (semi-) automatic
parallelization of adaptive streaming applications. This will allow
designers to extract parallelism from applications specified as
sequential programs, in a short amount of time. This will be speeding
up significantly the derivation of parallel specifications,
i.e. Parameterized KPNs, for adaptive streaming
applications. Currently such derivation is one of the most time
consuming design efforts. Furthermore to exploit efficiently the
parallelism captured in Parameterized KPNs, it is necessary to have
techniques for mapping them onto MPSoCs. Therefore, design time tools
will be developed for efficient mapping of multiple (dynamic)
streaming applications modeled/specified as Parameterized KPNs onto a
single MPSoC. To ensure successful accomplishment of the research and
development tasks mentioned above as well as to enable quick and easy
dissemination of the results, the PhD student will not develop
completely new tools but he/she will extend substantially already
existing tools developed at LIACS, Leiden University such as KPNgen
and ESPAM which are part of the DAEDALUS framework
(http://daedalus.liacs.nl) for System-level design of MPSoCs.
———————————————————————-

Job Requirements:
———————————————————————-
University Graduate

Applicants are expected to have a university degree (MSc), preferably
in Computer Science or Computer (Electrical) Engineering. Applicants
must also be proficient in spoken and written English.
———————————————————————-

Organization:
———————————————————————-
Leiden Institute of Advanced Computer Science, Leiden University, The
Netherlands

The PhD research will be carried out in the Leiden Embedded Research
Center (LERC) at the Leiden Institute of Advanced Computer Science,
Leiden University. LERC is an expert group and an internationally
recognized leader in advanced research in Embedded Systems and
Software. The group covers two related topics in this rapidly evolving
domain: 1) Embedded Systems theory and applications; 2) Embedded
Systems Design – methods, techniques, CAD tools and toolflows.
LERC’s application domains are signal processing, multimedia,
communications, smart cameras, computer vision, and graphics. The
research at LERC deals with abstract application models,
platform/architecture models, and mapping models in these domains, at
various levels of abstraction, for performance analysis, exploration
and design, conceptually and practically, down to real platform/system
implementations. The main mission of LERC is by its research to
contribute in a highly innovative way to the system-level design of
embedded systems and software – conceptually (theory),
methodologically (design methods and tools), and structurally
(platforms/architectures). Finally, LERC is advocating and applying
state-of-the-art Software Engineering Techniques both in the way the
group’s projects are integrated, documented, and assessed, and in the
way CAD software tools are written, tested and assessed. All this
justifies the LERC belief that "The CAD software is the Publication"
that makes significant impact in the research and industrial
community. In this respect, one of the LERC research achievements is
the DAEDALUS open source framework for automated design, programming,
and implementation of multi-processor embedded systems, targeting
streaming multimedia applications. It can be found at
http://daedalus.liacs.nl/. One of the LERC achievements regarding the
dissemination of research results to the industry is a professional
tool-flow to go very fast from applications specified in Matlab or C
to highly efficient implementations of these applications in
heterogeneous multi-core platforms. Part of this tool-flow was moved
to a start-up company called CompaanDesign BV
(http://www.compaandesign.com/).
———————————————————————-

Conditions of Employment:
———————————————————————-
Employment conditions (salary, benefits, etc.) are in accordance with
the Collective Labour Agreement for Dutch Universities.

Maximum salary amount in Euro’s a month: 2612

Employment basis: Temporary for specified period

Duration of the contract: Initially, the successful applicant will be
appointed for one year. Then after a positive evaluation, the
applicant will be appointed for a fixed-term period of three years.

Maximum hours per week: 38
———————————————————————-

Additional Information:
———————————————————————-
Additional information about the PhD position can be obtained from:

Dr.ir. Todor Plamenov Stefanov
Assistant Professor           
Phone : +31-(0)71-527-5775   
Fax   : +31-(0)71-527-6985   
E-mail: stefanov@liacs.nl     
Web-page: http://www.liacs.nl/~stefanov/
———————————————————————-

How to apply:
———————————————————————-
You can apply for this PhD position before 31-08-2009 by sending your
application electronically to:

Dr.ir. Todor Plamenov Stefanov
E-mail: stefanov@liacs.nl     

The application should include a Curriculum Vitae, a Letter of
Motivation, and a MSc diploma with transcripts (courses + grades).
———————————————————————-

** Deadline May 18th, 2009 **

We’re pleased to announce a call for proposals for this year’s HiPEAC PhD Collaboration Grants. These grants are available to all HiPEAC PhD students and junior post-doctoral researchers. Each grant will provide 5000 euros for a 3 month collaborative visit.

The origin or destination institution has to be a HiPEAC member.

The application process is simple and straightforward. Please complete the web page at http://www.hipeac.net/collaboration_grants where we would like the following information (max 1000 words)

- Applicant’s name and institution

- Proposed site and researcher to visit

- Estimate of collaboration start date

- Work to be performed

Plus

- A statement of why a 3 month visit would be useful (max 100 words)

- Applicant’s CV

The work to be performed should be a short description of the proposed work, what it is hoped will be achieved, its relevance to HiPEAC and how it contributes to HiPEAC’s goals.

Priority will be given to those applications judged likely to lead to high quality joint publications.

The successful candidates will be informed by end of June

Best Regards

Michael O’Boyle

–

The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336.

The Universal Parallel Computing Research Center (UPCRC) at the University of Illinois at Urbana-Champaign, a joint research endeavor with Microsoft Corporation and Intel Corporation, is seeking Postdoctoral Research Associate candidates. The Center brings together researchers in computer science and computer engineering to discover easy and accessible methods for programming multicore computing systems.

The qualified candidate must have strong research experience in programming languages for parallel computing. The work will involve language design and implementation. Research experience in compilers and parallel programming is required. The research will be pursued in collaboration with Professor Marc Snir and other faculty and students in UPCRC and the Department of Computer Science.

The position is for one year, extendible to a second year. Salary is commensurate with experience.

For full consideration please send a cover letter, resume and 3 professional references via email to Professor Marc Snir (snir@illinois.edu) prior to 5/31/09.

Chalmers University of Technology announces
a Position for Ph.D. study
in the field of Computer Architecture
at the Department of Computer Science and Engineering
Application deadline April 17, 2009
The High-Performance Computer Architecture Group is conducting research on design principles for the next generations of mainstream as well as embedded high-performance computers. To ease the programming task and yet achieve a high computational performance at as high energy efficiency as possible are important objectives in the knowledge generation process that the group contributes to. To this end, the group has a solid track record in contributing to design principles of parallel computers and a current focus is on multi-core computers.
The group participates in the HiPEAC European Network of Excellence as a partner and in two European projects that focus on multi-core architectures. A driving theme regards the definition and implementation of new hardware/software interfaces to ease the task of designing software for exploiting the computational performance of multi-core computers.
Aim of work
The PhD student shall participate in a project that concerns novel execution models for multicore computers. Known execution models lead to significant efforts in rewriting existing software. The project aims at exploring ways to extract parallelism dynamically so that the parallelism offered by multicore computers can be exploited.
Applicants
shall have a Master’s Degree or corresponding (sw. civilingenjörsexamen) in Computer Science, Computer Engineering, or Electrical Engineering or in a related discipline. As for all PhD studies, a genuine interest and curiosity in the subject matter and excellent analytical and communication skills, orally as well as literally, are needed. Further, since the research work normally involves developing simulation models of detailed computer architectures, good programming skills are important. A successful candidate must have a profound interest in computer architecture and a foundation in design principles of processors and memory systems.
In order to improve gender balance, Chalmers welcomes in particular applications from female candidates.
Details about employment
The appointee must also have been admitted to Chalmers Doctoral Programme. PhD student positions are limited to five years and will then normally include 20% departmental work, mostly teaching duties. Admission and employment are regulated in Chalmers’ “Rules of Procedure for Doctoral Programmes”, §4 and §5. Salary follows the agreement for PhD student positions.
Further information
Research level: Professor Per Stenström (www.ce.chalmers.se/~pers)
tel. 031-772 1761, e-post: pers@chalmers.se or
Departmental level:, Associate Professor Lars Svensson,
tel. 031-772 1704, e-post: larssv@chalmers.se
More information is available at the departmental homepage
Your application
shall consist of a cover letter with the reference number 2009/28 stated, a complete CV, copies of exam diploma with grades and other documents you wish to refer to.
Closing date for the application is April 17, 2009.
The application should preferably be sent by email to: registrator@chalmers.se or by surface mail to:
Registrator
Chalmers University of Technology
SE-412 96 Göteborg, Sweden
Phone via Chalmers exchange: +46 31 772 10 00
Fax registrar: +46 31 772 49 22
Please, don’t send your application to the above mentioned professor or head of department.
Union representatives
SACO Jan Lindér
ST-ATF Marie Wenander
SEKO Ralf Berndtsson
All reachable via Chalmers exchange: +46 31 772 10 00