Post-doc position available at INRIA DART group
5 03 2010Title of the proposal: Efficient Resource Utilization in Dynamically Reconfigurable Multi-processor Embedded Systems
Keywords: Reconfigurable (FPGA) Systems, Partial and dynamic reconfiguration, programming/execution model, Multi-cores, Embedded architectures, energy/power consumption saving.
Author of the proposal: Jean-Luc Dekeyser, Smail Niar, Samy Meftali
Supervisor of the Post-doc: Jean-Luc Dekeyser, Smail Niar, Samy Meftali
Team-Project: DART
Location: LILLE
Scientific context:
The computing industry is trying to improve embedded system performances with parallel execution and reconfigurability[1][2]. If the trend towards the use of multi-cores systems does not need to demonstrate, the use of reconfigurable circuits (RC) is much more recent. This solution represents an alternative to GPPs and ASICs as it offers a good compromise between the GPP flexibility and ASICs performances. Thanks to the technological evolution, the number of logical cells has strongly augmented. The recent Virtex6 Xilinx FPGA family for instance contains 6 times more logical elements and DSPs than the VirtexII family [3] designed 6 years ago, all with a 60% power consumption reduction. According to the ITRS [2] this tendency will grow in the coming years. It will be then possible over the years to put on a RC, hundreds of processors with their interconnection network [4][5].
Another benefit in the use of RCs is their ability to offer partially and dynamic reconfiguration. In the area of MPSoC, this feature can be used to add specialized computing cores on the FPGAs function of the application parameters and running conditions. FPGA flexibility thus allows programmers to reconfigure them as needed. Consequently, multiple low-frequency heterogeneous cores and IPs can be used to provide further power savings by specialization. As a result, customized programmable hardware can significantly improve the execution speed with lower energy budget [6][7].
Goal:
In spite of these achievements, programming and efficient exploitation of these dynamically RC remains a painful and complicated task.
For instance in the past the vast majority of FPGA users were hardware designers with an important amount of knowledge and experience in circuit design. VHDL or Verilog are the most used languages to program these FPGA. These languages are however unfamiliar to the majority of SoC software programmers. In addition, the management of partially dynamically reconfigurable circuits with the existing tools does not allow an efficient and an easy use of the huge FPGA possibilities.
The objective of this post-doc is to collaborate in designing a methodology for a better and easy utilization of current and future FPGA hardware resources. The post doctor must lead to the proposal of a new programming and execution model specific to multi-processor architecture systems on FPGA. Heterogeneity and dynamic reconfigurability are the main features that must be taken into account.
To allow an efficient and dynamic control of the system resources, the model must define new services either at the operating system level or at the hardware level (performance monitoring unit). Through these services, it will be possible for the developer to determine at run time the state of the system and the application needs. This may correspond to application energy consumption, cache or memory activities, and workload at the NoC level, etc. On the other side, and by the using of this information, the application developer will be able to control the dynamic application deployment on the architecture.
Required skills:
Candidates must have (or are about to receive) a Ph.D. in the domain of Embedded Sw or Hw design. He/She must have a strong background either in parallel programming models or in reconfigurable embedded system design.
To apply, please visit:
Bilbiographical References:
1. 1 M.Duranton and Al., Hipeac roadmap, 2009
http://www.hipeac.net/system/files/lr_3128_hipeac_roadmap-2009-v5.pdf
2. 2 www.itrs.com
3. 3 www.xilinx.com
4. 4 www.eve.com
5. 5 X.Li and O.Hammami, Fast Design Productivity for Embedded Multiprocessor through Multi-FPGA Emulation: The case of a 48-way Multiprocessor with NOC.
6. 6 R. Wain et Al., An overview of FPGAs and FPGA programming, internal technical report, CCLRC Daresbury Laboratory, 2006.
7. 7 A.Donlin, Applications, Design Tools and Low Power Issues in FPGA Reconfiguration, in “Designing Embedded Processors” book.
8. 8 V.M. Sima , K. Bertels, Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform, 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS’09).
Categories : Post-doc





