Call for Papers

First Workshop on I/O Virtualization (WIOV \’08) December 10-11, 2008, San D= iego, CA, USA www.usenix.org/wiov08
WIOV \’08 will be held in conjunction with the 8th USENIX Symposium on Opera= ting Systems Design and Implementation (OSDI \’08), December 8-10, 2008.

Overview

Over the past decade, the use of virtualization technology has grown rapidl= y. Moreover, it is being used in a variety of places, ranging from the data= center to the desktop. Although this has spurred great advances in process= or and memory virtualization in commodity hardware and virtualization softw= are, I/O virtualization has received far less attention. However, both pers= onal computers and servers may perform significant amounts of I/O. For exam= ple, efficient virtualization of graphics hardware has presented significan= t challenges on the desktop and efficient virtualization of network interfa= ces has limited server consolidation in the data center.

This workshop is meant to provide a forum to discuss challenges of I/O virt= ualization that span the virtual machine monitor, guest operating system, p= rocessor, memory subsystem, and I/O subsystem. In that spirit, we welcome p= apers that describe new challenges in I/O virtualization and papers that de= scribe novel approaches to solving known problems in I/O virtualization. Th= e final program will consist of both reviewed submissions and invited talks= . The invited talks will focus on open problems in I/O virtualization and w= ill be accessible to a broad audience.

Topics of interest include but are not limited to:

* Hardware support for I/O virtualization
* Novel I/O device architectures for virtualization
* Novel software approaches to I/O virtualization
* Software methods for I/O device emulation
* Para-virtualized I/O device driver design for virtualization * Virtual machine monitors I/O subsystems
Important Dates

Submissions due: September 15, 2008
Notification to authors: October 3, 2008 Final files due: November 3, 2008
Workshop Organizers

Program Co-Chairs

Muli Ben-Yehuda, IBM Haifa Research Lab
Alan L. Cox, Rice University
Scott Rixner, Rice University

Program Committee

Eyal de Lara, University of Toronto
Jun Nakajima, Intel
Renato Santos, HP Labs
Karsten Schwan, Georgia Institute of Technology
Pratap Subrahmanyam, Vmware
Leendert van Doorn, AMD
Andrew Warfield, University of British Columbia

Submission Guidelines

Please submit an extended abstract in PDF format through the workshop submi= ssion web form, which will be available at www.usenix.org/wiov08 soon. The extended abstract should be no more = than 4 double-column pages using 10-point type on 12-point leading (\”single= -spaced\”). Figures and references are not included in this 4-page limit.

–
Workshop on I/O Virtualization (WIOV \’08) Co-located with OSDI \’08, Dec 200= 8, San Diego, CA www.usenix.org/wiov08

==========================
==========================
======================
Call for Papers
MPSoC and System Design Methods
Topic D2 @ DATE 2009
Nice, France
April 20-24, 2009
=
==========================
==========================
======================

Papers are solicited in the areas of multi-core SoC architecture, including= in particular the simulation and design of multi-core SoC.
We are also looking for contributions devoted to electronic system- level d= esign methods, tool flows and their practical application, including applic= ation-specific design methodologies, particularly for embedded hardware and= software, or targeted specification, modeling, and validation flows. Final= ly, the topic will also cover design reuse and platform design support tool= s.

SUBMISSION INSTRUCTIONS
All manuscripts must be submitted electronically before September 7th, 2008= , following the instructions on the conference Web page: www.date-conference.com The accepted file formats are PDF and Postscript. Manuscripts received in h= ard-copy form will not be processed.
Papers can be submitted for either standard oral presentation or for intera= ctive presentation. Standard oral presentations require novel and complete = research work supported by experimental results, and are held in front of a= full audience. Besides these, DATE will again include interactive presenta= tions of novel ideas that may require additional research or lack experimen= tal data. Presentations are given on a laptop in a face-to-face discussion = area.
Submissions should not exceed 6 pages in length for oral-presentation and 4= pages in length for interactive-presentation papers, and should be formatt= ed as close as possible to the final format: A4 or letter sheets, double co= lumn, single spaced, Times or equivalent font of minimum 10pt (templates ar= e available on the DATE Web site for your convenience). To permit blind rev= iew, submissions should not include the author names. Any submission not i= n line with the above rules will be discarded.
All papers will be evaluated with regard to their suitability for the confe= rence, originality and technical soundness. The Programme Committee reserve= s the right to accept interesting contributions that do not meet the criter= ia for standard oral presentations, as interactive presentations.

TOPIC CHAIRS
Luciano Lavagno
Politecnico di Torino, Dipartimento di Elettronica Corso Duca degli Abruzzi= 24, 10129 Torino, Italy e-mail: luciano.lavagno @polito.it

***************************************************************************=
*****
CALL FOR PAPERS

3rd Workshop on

Statistical and Machine learning approaches
to ARchitecture and compilaTion
(SMART\’09)

www.hipeac.net/smart-workshop.html

January 25, 2009, Paphos, Cyprus

(co-located with HiPEAC 2009 Conference)

**** PUBLICATION INFORMATION ****

Selected papers will be considered for publication in a special issue of the International Journal of Parallel Programming.
***************************************************************************=
*****

The rapid rate of architectural change and the large diversity
of architecture features has made it increasingly difficult
for compiler writers to keep pace with microprocessor evolution.
This problem has been compounded by the introduction of multicores.
Thus, compiler writers have an intractably complex problem to solve.
A similar situation arises in processor design where new approaches are needed to help computer architects make the best use of new underlying technologies and to design systems well adapted to futureapplication domain= s.

Recent studies have shown the great potential of statistical machine learning and search strategies for compilation and machine design.
The purpose of this workshop is to help consolidate and advance the state of the art in this emerging area of research. The workshop is a forum for the presentation of recent developments in compiler techniques and machine design methodologies based on space exploration and statistical machine learning approaches with the objective of improving performance, parallelism, scalability, and adaptability.

Topics of interest include (but are not limited to):

Machine Learning, Statistical Approaches, or Search applied to

* Feedback-Directed Compilation
* Auto-tuning Programs + Language Extensions
* Library Generators
* Iterative Compilation
* Dynamic Compilation/Adaptive Execution
* Parallel Compiler Optimizations
* Low-power Optimizations
* Simulation
* Performance Models
* Adaptive Processor and System Architecture
* Design Space Exploration
* Other Topics relevant to Intelligent and Adaptive Compilers/Architectures

**** Paper Submission Guidelines ****

Paper length – maximum 15 pages. Papers must be submitted in the PDF (preferably) or postscript formats using the workshop submission website: unidapt.org/dissemination/workshops/smart09
An informal collection of the papers to be presented will be distributed at the workshop. All accepted papers will appear on the workshop website.

**** Important Dates ****

Deadline for submission: November 7, 2008
Decision notification: December 19, 2008
Workshop: January 25, 2009

Program Chair:
David Padua, University of Illinois at Urbana-Champaign, USA

Organizers:
Grigori Fursin, INRIA Saclay, France
John Cavazos, University of Delaware, USA

Program Committee:
Saman Amarasinghe, MIT, USA
Francois Bodin, CAPS Enterprise, France
Calin Cascaval, IBM T.J. Watson Research Center, USA
John Cavazos, University of Delaware, USA
Franz Franchetti, Carnegie Mellon University, USA
Ari Freund, IBM Haifa Research Lab, Israel
Grigori Fursin, INRIA Saclay, France
Mary Hall, USC/ISI, USA
Robert Hundt, Google, USA
Michael O\’Boyle, University of Edinburgh, UK
David Padua, University of Illinois at Urbana-Champaign, USA
Richard Vuduc, Georgia Institute of Technology, USA
David Whalley, Florida State University, USA

==========================
==========================
==========================
=====

12th International Workshop on
Software and Compilers for Embedded Systems

SCOPES 2009

April 23-24, 2009
Acropolis, Nice, France

www.scopesconf.org

—————————————————————————= —–
CALL FOR PAPERS

==========================
==========================
==========================
=====

ABOUT SCOPES 2009

The influence of embedded systems is constantly growing. Increasingly power= ful and versatile devices are developed and put on the market at a fast pace. T= he number of features is increasing, and so are the constraints on the systems concerning size, performance, energy dissipation and timing predictability.
Since most systems today use a processor to execute an application program rather than using dedicated hardware, the requirements can not be fulfilled= by hardware architects alone: Hardware and software have to work together to m= eet the tight constraints put on modern devices.

One of the key characteristics of embedded software is that it heavily depe= nds on the underlying hardware. The reason of the dependency is that embedded software needs to be designed in an application specific way. To reduce the system design cost, e.g. code size, energy consumption etc., embedded softw= are needs to be optimized exploiting the characteristics of the underlying hardware.

SCOPES focuses on the software generation process for modern embedded syste= ms.
Topics of interest include all aspects of the compilation process, starting with suitable modeling and specification techniques and programming languag= es for embedded systems. The emphasis of the workshop lies on code generation techniques for embedded processors. The exploitation of specialized instruction set characteristics is as important as the development of new optimizations for embedded application domains. Cost criteria for the entir= e code generation and optimization process include runtime, timing predictability, energy dissipation, code size and others. Since today\’s embedded devices frequently consist of a multi-processor system-on-chip, th= e scope of this workshop is not limited to single-processor systems but particularly covers compilation techniques for MPSoC architectures.

In addition, this workshop intends to put a spotlight on the interactions between compilers and other components in the embedded system design proces= s.
This includes compiler support for e.g. architecture exploration during HW/= SW codesign or interactions between operating systems and compilation techniqu= es.
Finally, techniques for compiler aided profiling, measurement, debugging an= d validation of embedded software are also covered by this workshop, because stability of embedded software is mandatory.

SCOPES 2009 is the 12th workshop in a series of workshops initially called \”International Workshop on Code Generation for Embedded Processors\”. The na= me SCOPES has been used since the 4th workshop. The scope of the workshop rema= ins software for embedded systems with emphasis on code generation (compilers) = for embedded processors. SCOPES will be held in cooperation with ACM SIGBED and= is sponsored by EDAA and PREDATOR. SCOPES 2009 is co-located with the DATE conference.

—————————————————————————= —–

IMPORTANT DATES

Full paper submission: Nov 21, 2008
Notification of acceptance: Jan 21, 2009
Final paper submission: Mar 02, 2009

—————————————————————————= —–

SUBMISSION INSTRUCTIONS

Papers should present original research results not published or submitted = for publication in other forums. Papers should not exceed 10 pages (single-spac= ed, 2 columns, 10pt font; see the DATE website www.date-conference.com for detailed guidelines) and must be submitted using the SCOPES paper submissio= n website. To permit blind review, submissions should not include the author names. Accepted papers will be published via the ACM digital library.

—————————————————————————= —–

GENERAL CHAIR

Heiko Falk
Computer Science 12
Dortmund University of Technology, DE

PUBLICITY CHAIR

Peter Marwedel
Computer Science 12
Dortmund University of Technology, DE

PROGRAM COMMITTEE

Twan Basten
TU Eindhoven, NL

Marco Bekooij
NXP semiconductors, NL

Trevor Carlson
IMEC Leuven, BE

Alain Darte
ENS Lyon, FR

Koen de Bosschere
University of Gent, BE

Nikil Dutt
University of Irvine, USA

J=F6rg Henkel
University of Karlsruhe, DE

Daniel K=E4stner
AbsInt GmbH, DE

Paul Kelly
Imperial College London, UK

Andreas Krall
TU Vienna, AT

Christian Lengauer
University of Passau, DE

Annie Liu
Stony Brook University, USA

Bilha Mendelson
IBM Research Lab, IL

Michael O\’Boyle
University of Edinburgh, UK

Yunheung Paek
Seoul National University, KR

J=FCrgen Teich
University of Erlangen, DE

Hans van Someren
ACE bv, NL

Reinhard Wilhelm
University of Saarbr=FCcken, DE

—————————————————————————= —–

FURTHER INFORMATION

Website: www.scopesconf.org
Mailing List: www.scopesconf.org/list

—————————————————————————= —–

SPONSORS

SCOPES 2009 is kindly supported and sponsored by the following companies an= d institutions:
+ ACM SIGBED
www.acm.org/sigbed

+ European Design and Automation Association, EDAA
www.edaa.com

+ PREDATOR European 7th Framework Project
www.predator-project.eu

—————————————————————————= —–
scopes09@ls12.cs.tu-dortmund.de

Call for Papers

22nd International Conference on

Architecture of Computing Systems ARCS 2009

– System Architecture and Energy Awareness -

held from March, 10th to March 13th in Delft, The Netherlands
Submission deadline October 10th

The ARCS series of conferences has over 30 years of tradition
reporting top notch results in computer architecture and
operating systems research. This year\’s focus is energy
awareness viewed from two different ways Firstly, this deals
with the improvement of computer systems to be as energy
efficient as possible (particularly for specific applications).
One can think of heterogeneous multi-core architectures or
reconfigurable architectures for this purpose. Secondly, this
addresses the usage of computer systems to reduce the energy
consumption of other systems, which might lead to problems of
communication and cooperation. Both aspects are relevant for
the conference. Like the previous conferences in this series,
it continues to be an important forum for computer architecture research. In 2009 ARCS will be hosted by the Delft University of Technology, which has one of the leading information technology schools in Europe. The proceedings of ARCS 2009 will be published in the Springer Lecture Notes on Computer Science (LNCS) series (pending). After the conference, authors of selected papers will be invited to submit an extended version
of their contribution for publication in a special issue of the Journal of Systems Architecture. Also, a best paper and best presentation award will be presented at the conference.

Paper submission
================
Authors are invited to submit original, unpublished research
papers on one of the following topics:
- Energy-awareness, green computing.
- Computer architecture topics such as multi-cores, memory
systems, and parallel computing.
- Adaptive system architectures such as reconfigurable systems
in hardware and software.
- Operating Systems including but not limited to scheduling,
memory management, power management, and RTOS.
- System aspects of ubiquitous and pervasive computing such as
sensor nodes, novel input/output devices, novel computing
platforms, architecture modeling, and middleware.
- Organic and Autonomic Computing including both theoretical
and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques.
- Embedded systems including but not limited to architecture,
communication, design methodologies, and applications.
- Network Centric and Grid Computing issues with a focus on
middleware.

Submissions should be done through the link provided at the
conference website www.ida.ing.tu-bs.de/arcs09/. Papers
should be submitted in pdf or postscript format. They should be formatted according to Springer LNCS style and not exceed 12 pages (see: www.springer.de/comp/lncs/authors.html)
Workshop and Tutorial Proposals
==========================
======
Proposals for workshops and tutorials within the technical
scope of the conference are solicited. Submissions should be
done through email directly to the workshops and tutorials
chair J=F6rg H=E4hner (haehner@sra.uni-hannover.de).

Important Dates
===============
Paper submission deadline: 10th October 2008
Notification of acceptance: 28th November 2008
Camera ready papers: 12th December 2008

General Chairs
==============
Mladen Berekovic, TU Braunschweig, DE
Christian M=FCller-Schloer, University of Hannover, DE

Program Chairs
==============
Christian Hochberger, Technische Universit=E4t Dresden, DE
Stephan Wong, Delft University of Technology, NL

Workshop and Tutorial Chair
==========================
==
J=F6rg H=E4hner, University of Hannover, DE

**************************************************
Call for Papers
SPEC 2009
**************************************************

January 25, 2009
Austin, Texas
www.spec.org/workshops/2009/austin/

The goal of the SPEC 2009 Workshop is to provide a forum for academia and industry to discuss the practice of system performance evaluation by the sharing of ideas and experiences. The workshop will bring together developers and users of performance evaluation software and will be held on Sunday, January 25, 2009 in Austin, Texas, in conjunction with SPEC\’s Annual meeting.

Presentations will center on novel performance evaluation strategies; new benchmark design; use of benchmarks in industry, academia and government; and workload characterization. While traditional areas of performance evaluation are solicited, papers addressing the emerging areas related to evaluating power, reliability, virtualization scalability and security are also of interest.

Standard Performance Evaluation Corporation, (SPEC) invites the performance evaluation community to submit full papers and extended abstracts on a range of topics relevant to performance evaluation. The proceedings will be published by Springer-Verlag (pending approval).

Submission guidelines:
Full (20 page) and short (8 page) papers are solicited. Submissions should be formatted according to the LNCS format (see author\’s instructions given on www.springer.de/comp/lncs/authors.html).
Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this workshop. Papers must be submitted electronically in PDF format.

Important Dates:
Paper/extended abstract Submission: October 3, 2008
Notification of Acceptances: October 26, 2008
Final Version of Papers: November 9, 2009
Workshop: January 25, 2009

General Chair: Rudi Eigenmann Purdue University
Program Chair: David Kaeli Northeastern University
Publication Chair: Kai Sachs TU Darmstadt

Program Committee
Jose Nelson Amaral – University of Alberta
Umesh Bellur – Indian Institute of Technology Bombay
Tom Conte – Georgia Tech
Anton Chernoff – AMD
Lieven Eeckhout – University of Ghent
Rudi Eigenmann – Purdue University
Jose Gonzalez – Intel Barcelona
John Henning – Sun Microsystems
Lizy John – University of Texas at Austin
David Kaeli – Northeastern University
Helen Karatza – Aristotle University of Thessaloniki
Samuel Kounev – Universitt Karlsruhe (TH)
Tao Li – University of Florida
David Lilja – University of Minnesota
Christoph Lindemann – University of Leipzig
John Mashey – Consultant
Jeffrey Reilly – Intel
Resit Sendag – University of Rhode Island
Erich Strohmaier – Lawrence Berkeley National Labs
Bronis Supinski – Lawrence Livermore National Labs
Petr Tuma – Charles University in Prague

Steering Committee:
Alan Adamson – IBM Canada
Jose Nelson Amaral – University of Alberta
David Bader – Georgia Tech
Rudi Eigenmann – Purdue University
Rema Hariharan – AMD
John Henning – Sun Microsystems
Lizy John – University of Texas at Austin
David Kaeli – Northeastern University
Samuel Kounev – Universitt Karlsruhe (TH)
David Morse – Dell
Kai Sachs – TU Darmstadt

Held in Cooperation with:

IEEE Technical Committee on Computer Architecture (TCCA)

International Symposium on Performance Analysis of Systems and Software
ISPASS-2009
Boston, MA
April 19-21, 2009

Sponsored by the IEEE Computer Society?s TCI, TCCA, and TC-uARCH

The IEEE International Symposium on Performance Analysis of Systems and Software provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software.
Authors are invited to submit previously unpublished work for possible presentation at the conference.

Papers are solicited in fields that include the following:

* Performance evaluation methodologies
o Analytical modeling
o Statistical approaches
o Tracing and profiling tools
o Simulation techniques
o Hardware (e.g., FPGA) accelerated simulation
o Hardware performance counter architectures
* Performance analysis
o Performance metrics
o Bottleneck identification and analysis
o Visualization
* Performance analysis of commercial and experimental hardware
o General-purpose microprocessors
o Multi-threaded, multi-core and many-core architectures
o Accelerators and graphics processing units
o Embedded and mobile systems
o Enterprise systems and data centers
o Supercomputers
o Computer networks
* Performance analysis of emerging workloads and software
o Software written in managed languages
o Virtualization and consolidation workloads
o Internet-sector workloads
o Embedded, multimedia, games, telepresence
o Bioinformatics, life sciences, security, biometrics
* Application and system code tuning and optimization
* Confirmations or refutations of important prior results

Next to *research papers*, we also welcome *tool papers* in order to reward tool-building effort and publicize new tools to the community. Tool papers will be judged more so on their potentially wide impact and use than on their research contribution. Tools in any of the above fields of interest are eligible.

See www.ispass.org for submission details.

***************************************************************************=
****

IMPORTANT DATES

Abstract due: Oct 3, 2008
Full submission: Oct 10, 2008 ? NO EXTENSION
Rebuttal: Dec 4-5, 2008
Notification: Dec 17, 2008
Final paper due: Feb 25, 2009

***************************************************************************=
****

ORGANIZING COMMITTEE

GENERAL CHAIRS
Dean Tullsen, UC San Diego
Todd Austin, University of Michigan

PROGRAM CHAIR
Lieven Eeckhout, Ghent University

PROGRAM COMMITTEE
Tor Aamodt, University of British Columbia
Steve Blackburn, Australian National University
Pradip Bose, IBM Research
David Brooks, Harvard University
Derek Chiou, University of Texas at Austin
Bronis R. de Supinski, LLNL
Sudhanva Gurumurthi, University of Virginia
Greg Hamerly, Baylor University
Ravishankar Iyer, Intel
Aamer Jaleel, Intel
Stefanos Kaxiras, University of Patras
Rakesh Kumar, UIUC
Benjamin Lee, Microsoft Research
Charles Lefurgy, IBM
Mikko Lipasti, University of Wisconsin?Madison
Daniel Ortega, HP Labs
Steve Reinhardt, AMD
Scott Rixner, Rice University
Eric Rotenberg, NCSU
Andr=E9 Seznec, IRISA
Tim Sherwood, UC Santa Barbara
Allen Snavely, UC San Diego
Thomas Wenisch, University of Michigan

LOCAL ARRANGEMENTS CHAIR
TBD

PUBLICITY CHAIR
Elmoustapha Ould-Ahmed-Vall, Intel

FINANCE CHAIR
Nadeem Malik, IBM

WEB CHAIR
Byeong Kil Lee, TI

PUBLICATIONS CHAIR
Rakesh Kumar, UIUC

WORKSHOPS/TUTORIALS CHAIR
Jun Yang, University of Pittsburgh

REGISTRATION CHAIR
Rajeev Balasubramonian, University of Utah

SUBMISSION AND REVIEW WEB CHAIR
Michiel Ronsse, Ghent University

—————————————————————————— LAGrid08 – 2n Intl. Latin American Grid Workshop lagrid08.lncc.br —————————————————————————— in conjunction with 20th Intl. Symposium on Computer Architecture and High Performance Computing Campo Grande – Brazil October 29th – November 1st, 2008 —————————————————-
The goal of the Latin American Grid (LAGrid) workshop is to act as a forum for technical presentations of ongoing research, development and relevant activities in the area of Grid Infrastructures, Services and Applications, in the context of and/or in partnership with Latin America.
The event focuses on bringing together researchers and professionals actively working in this field, promoting multi-institutional collaborations between groups of diverse competences.

The LAGrid workshop gives particular attention to the Grid deployment initiatives in Latin America and the challenges they face as regards the distribution of and efficient access to scarce compute, storage and communication resources in this continent. Discussions and studies about new application areas and the potential impact of Grid technology in Latin America are also of main interest.

Authors are therefore particularly encouraged to submit reports about their experiences in deploying Grid Infrastructures, Services and Applications.
—————————————————-
Selected papers will be invited to submit extended versions to a Special Issue of Concurrency and Computation: Practice and Experience Journal.
—————————————————-
Deadlines
====================================================
Submisssion: September 1st – 2008
Communication to Authors: September 29th – 2008
Camera Ready: October 14th – 2008
—————————————————-
The areas of interest in LAGrid 2008 include, but are not limited to: ==================================================== * Cyberinfrastructures in Latin America; * Impact of Grid technology in Latin America;
* Applications for Latin America;
* Middleware solutions for Latin America;
* Promoting e-Science collaborations in Latin America;
* Funding models supporting Latin America cyberinfrastructures;
* Cost-effective solutions for Latin America;
* Grid economy models for Latin America;
* Role of Grids in broadening participation in science and education in
Latin America.
—————————————————-
Submission Format
====================================================
Authors should submit papers of no more than 6 pages in a two-column format.
The main text must be in 10-point Times, single-spaced. For further information refer to the author guidelines for IEEE CS 8.5 x 11-inch proceedings manuscripts. Authors should submit a PostScript (level 2) or PDF file that will print on a PostScript printer. Submission implies the willingness of at least one of the authors to register to the conference and workshop and present the paper. Submitted papers will be reviewed by at least 3 reviewers. Submission is electronic only at submissoes.sbc.org.br/Paper.cgi?c=717&track=1792 .
—————————————————-

Workshop Chairs:
Bruno Schulze – LNCC, BR
Francisco Brasileiro – UFCG, BR
—————-

CALL FOR PAPERS

Second Workshop on Programmability Issues for Multi-Core Computers
(MULTIPROG-2009)

Held in conjunction with the 4th International Conference on
High-Performance

and Embedded Architectures and Compilers (HiPEAC)

Paphos, Cyprus, January 25-28, 2009

Goal of the Workshop

——————–

Computer manufacturers have already embarked on the multi-core roadmap, promising
to double the number of processors on a chip every other year, and many-cores are
on the horizon. This shift to an increasing number of cores has placed new burdens
on the programming community. Until now, software has been developed with a single
processor in mind and it needs to be parallelized to take advantage of the new
breed of multi-/many-core computers. As a result, progress in how to easily harness
the computing power of multi-core architectures is in great demand.

This workshop aims to bring together, and cause fruitful interaction between,
researchers interested in programming models and their implementation and in

computer architecture with the common interest in advancing our knowledge how to
simplify the task of parallelization of software for multi-core platforms. A wide
spectrum of issues are central themes for this workshop such as what the future
programming models should look like to accelerate software productivity and how
it should be implemented at the runtime, the compiler, and the architecture level.

We will prioritize papers reporting on on-going work that address cross-cutting
issues and that provide thought-provoking insights into the main themes.
Proceedings

with accepted papers will be made available at the workshop. Selected papers will
appear on a special issue of Transactions on HiPEAC, after a new review process.

Topics of interest

——————

Papers are sought on topics including, but not limited to:

* Multi-core architectures

o Architectural support for compilers/programming models
o Processor (core) architecture and accelerators (GPUs, …)
o Memory system architecture

o Performance/power issues

* Programming models for multi-core architectures

o Language extensions

o Run-time systems

o Compiler optimizations and techniques

o Tools for discovering and understanding parallelism
* Applications for multi-core architectures

o Methodologies for developing applications

o Benchmarking

Organizers

———-

Eduard Ayguade Barcelona Supercomputing Center Spain (eduard[at] ac.upc.edu)
Roberto Gioiosa Barcelona Supercomputing Center Spain
(roberto.gioiosa[at]bsc.es)

Per Stenstrom Chalmers University of Technology Sweden (pers[at] chalmers.se)
Osman Unsal Barcelona Supercomputing Center Spain
(osman.unsal[at]bsc.es)

Important dates

—————

Submission deadline: Oct 10, 2008

Notification to authors: Nov 28, 2008

Final version of accepted papers: Dec 19, 2008

Paper submission

—————-

Submitted papers should use the LNCS format and should be 12 pages maximum.
Manuscript

preparation guidelines can be found at the LNCS web site (
www.springeronline.com/lncs,

go to -> For Authors -> Information for LNCS Authors). Submit your paper through the
MULTIPROG submission server (multiprog.ac.upc.edu/CRP/).

Program Committee

—————-

TBD

==========================
==========================
=======================
Call for Papers: NoCArc 2008
First International Workshop on Network on Chip Architectures To be held in conjunction with the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41) 8th November, 2008 Lake Como, Italy ==========================
==========================
=======================

General Information
——————-
Single chip embedded systems are becoming increasingly complex and heterogeneous. Such Systems-on-Chip (SoCs) require seamless integration of numerous IP cores performing different functions and operating at different clock frequencies. Network-on-Chip (NoC) is generally viewed as the ultimate solution for the design of modular and scalable communication architectures and provides inherent support to the integration of heterogeneous cores through the standardization of the network interfaces. This workshop is focused on issues related to design, analysis and testing of on-chip networks.

Areas of Interest
—————–
The topics of specific interest for the workshop include, but are not limited to:
* Architectures and Topologies for NoCs and MPSoCs
* Routing algorithms and Router Micro-architectures
* Fault tolerance, reliability and testing issues
* Dynamic on-chip network reconfiguration
* Modeling and evaluation of on-chip networks
* Design space exploration and tradeoff analysis
* On-chip interconnection network simulators and emulators
* Industrial case studies of SoC designs using the NoC paradigm

The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing \”work in progress\” or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Submission Guidelines
———————

The authors are invited to submit unpublished work related to
workshopss s theme. Both research and application-oriented papers are welcome. All papers should be submitted electronically via the workshop web-page at:
www.diit.unict.it/users/mpalesi/nocarc/.

Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Papers should be formatted in accordance with the templates published in the workshop webpage (standard double-column IEEE in A4 format). Submissions must be limited to 6 pages. If the authors wish a blind review to be performed, then the author\’s name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.

Important Dates
—————
Submission deadline 24th August, 2008
Author notification 1st October, 2008
Camera-ready version due 10th October, 2008
NoCArc Workshop 8th November, 2008

Workshop Organizers
——————-
* Maurizio Palesi
Dipartimento di Ingegneria Informatica e delle Telecomunicazioni University of Catania, Italy www.diit.unict.it/users/mpalesi
* Shashi Kumar
Department of Electronics and Computer Engineering
School of Engineering
J=F6nk=F6ping University, Sweden
hem.hj.se/~kush/

Program Committee
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* Federico Angiolini, iNoCs, Switzerland
* Davide Bertozzi, University of Ferrara, Italy
* Giorgos Dimitrakopoulos, FORTH, Greece
* Jos=E9 Flich Cardo, Universidad Polit=E9cnica de Valencia, Spain
* Ahmed Hemani, Royal Institute of Technology, Sweden
* Anshul Kumar, Indian Institute of Technology, India
* Marcello Lajolo, NEC Laboratories America, NJ, USA
* Zhonghai Lu, Royal Institute of Technology, Sweden
* Srinivasan Murali, EPFL, Switzerland and Stanford University, USA
* Juan Manuel Ordu=F1a Huertas, Universidad de Valencia, Spain
* Davide Patti, University of Catania, Italy
* Partha P. Pande, Washington State University, USA
* Timothy M. Pinkston, University of Southern California, USA
* Carlo Pistritto, STMicroelectronics, Italy
* Tor Skeie, University of Oslo, Norway
* Vittorio Zaccaria, Politecnico di Milano, Italy