Call for Papers

(Post-Doc) Researcher: Automatic architecture and circuit synthesis of adaptable ASIP-based SoCs

Eindhoven University of Technology

Faculty of Electrical Engineering

Eindhoven

The Netherlands

FTE 1.0

Application Deadline: 15-09-2010

Vacancy Number: V36.1075

The Faculty of Electrical Engineering delivers education and performs scientific and technological research in the broad discipline of Electrical Engineering. Electrical Engineering covers the application of electrical phenomena with respect to energy, information processing and telecommunication, as well as, electrical and electronic components, and the technology involved. Both hardware, in the form of electronic circuits and accessories, and software, in the form of system software for electro-technical applications, are the subject of study. Existing or new electrical devices, components and systems are analyzed, designed, implemented, controlled and realized. In addition, the maintenance of these systems is the subject of research, as is the societal relevance of electrical engineering and information technology.

Position

The position is in the Section of Digital Circuits and Formal Design Methods (DCFDM) of the Electronic Systems (ES) Group. The mission of the ES Group is to provide a scientific basis for design trajectories of digital electronic circuits and systems ‘from (generalized) algorithm to realization’. To identify the key problems, and verify the validity, robustness and completeness of our results, we develop, implement and maintain consistent and complete flows, and use them for realizing innovative hardware, with emphasis on video processing and embedded architectures. The mission of the DCFDM Section is research and development of theory, methods and EDA tools for modeling, analysis, synthesis and optimization of digital circuits and systems to adequately cope with the increasing complexity and challenges of the nano-electronic technologies. It has an internationally recognized expertise in design theory, methodology and electronic design automation for embedded system design and hardware synthesis. It has also experience with FPGA-based design, (re-)configurable architectures, multi-objective circuit and system optimization and automatic architecture synthesis for (heterogeneous) platform-based systems.

Project

The research work will be performed in the scope of the Architecture Synthesis and Application Mapping (ASAM) project, being a part of the European research program ARTEMIS. The ASAM project addresses the problem of an automatic coherent architecture synthesis and application mapping for heterogeneous multi-processor embedded systems based on configurable application-specific instruction-set processors (ASIPs). It aims at defining a new unified design methodology, as well as, related synthesis and prototyping tool-chains for: multi-objective design space exploration for configurable heterogeneous multi-ASIP systems and identification of the application-tailored system architectures; automatic architecture instantiation or customization of particular application-tailored processors, memories and communication structures of the system architecture; optimal hardware synthesis of the created platform; automatic application mapping on the resulting multi-processor heterogeneous platform; and software compiler retargeting and automatic software compilation, all when accounting for the platform hardware characteristics and for the functional and extra-functional requirements and trade-offs.

The research work will be focused on the automatic architecture instantiation or customization of the application-tailored ASIPs, including their extension with new application-specific instructions and related hardware, optimal synthesis of the ASIPs’ hardware, and collaboration of these micro-architecture and hardware synthesis tasks with the memory and communication architecture synthesis, as well as, with the macro-architecture synthesis of the whole heterogeneous multi-processor system.

Tasks

The main tasks include:

• research work in the scope of the above described project involving development of new design methods, and related electronic design automation (EDA) analysis and synthesis flows and tools, software implementation of the prototype EDA tools and flows, and experimental research with their use;
• assistance to the project coordinator in implementation of the coordination decisions, as well as, coordination, organization, communication and reporting activities, and in supervision of the junior researchers and students;
• establishing and adequately running of the project web-page.

Requirements

Candidates for this Post-doc researcher position should meet the following requirements:

• MSc in Embedded Systems, Computer Engineering, Electronics, Electrical Engineering, Information Technology or related area, with an advanced knowledge or minor/majors in subjects related to electronic design automation, (embedded) processor architectures and/or SoC design;
• Ph.D. degree preferably or P.D. Eng. Degree and an equivalent amount of experience, or MSc degree and a proven large amount of experience and substantial achievements in research and development related to electronic design automation, (embedded) processor architectures and/or SoC design;
• a solid knowledge of and substantial experience in software design and programming, including knowledge of and experience with programming in C++ and/or C;
• excellent invention and learning abilities;
• excellent analytical, organizational and communication skills, including an ability of effective and efficient individual work, as well as, easy cooperation in a team with supervisors, students, other researchers and companies, and excellent English language capabilities both in writing and speaking;
• a substantial knowledge of or experience with ASIP processors, instruction-set synthesis, (re-)configurable systems, FPGA-based design and prototyping, and related EDA tools will be a premium.

Appointment and Salary

The appointment is of immediately and can start as soon as possible. The appointment will be for three years. The gross monthly salary will be in accordance with the Collective Labor agreement of the Dutch Universities (CAO NU) and amounts to at least € 2861 per month (initially, scale 10.4) depending on prior experience. An offer will be based on your knowledge and experience. An attractive package of fringe benefits (including excellent work facilities, end of the year allowance and sport facilities). Moreover an 8% bonus share (holiday supplement) is provided annually.

Information

For more information on the project, tasks or requirements please contact Dr. ir. L. Józwiak, tel. +31-(0)40-2473645, e-mail: L.Jozwiak@tue.nl.

For terms on employment please contact: Mr. P.F.M. Tiel Groenestege, HR advisor of the Faculty of Electrical Engineering tel. +31-(0)40-2472004, e-mail: p.f.m.tiel.groenestege@tue.nl .

More information and on-line application form can be found on the TU/e web-pages:

http://jobs.tue.nl/wd/plsql/wd_portal.search_results?p_web_site_id=3085&p_category_id=3713&p_show_results=Y&p_form_type=CHECKBOX&p_no_days=999&p1=6047&p1_val=Any&p2=6048&p2_val=Department+of+Electrical+Engineering&p_text=&p_save_search=N

and

http://w3.tue.nl/en/services/dpo/excellent_jobs_for_excellent_people

The newly established ExaScience Lab is a research partnership between Intel, five Belgian (Flemish) universities and the IMEC research institute, and brings together researchers in physics, numerical solvers and parallel programming, architectural simulation and modeling, and visualization. The Lab?s mission is to design and develop algorithms, tools and software methods for future exascale computing targeted towards space weather modeling and other scientific applications, and to design and develop architectural simulation and modeling techniques for projecting performance, power and reliability estimates of future exascale systems. ExaScience Lab is part of Intel Labs Europe.

The research group led by Prof. Lieven Eeckhout at the Department of Electronics and Information Systems at Ghent University is a partner in the ExaScience Lab and focuses on architectural simulation and modeling of future exascale systems. New architectural modeling and simulation approaches will be developed as well as workload scale-down and scale-up methodologies in order for architects to enable making design decisions and explore the architectural design space of future exascale systems.

There are two open post-doctoral research positions for highly motivated individuals: one for immediate start and one for Jan 2011.

Candidates should have strong backgrounds in at least one of the following areas:

? Computer architecture

? Architectural simulation and modeling

? Power and reliability modeling

? Workload analysis and characterization

? Scientific computing

The researchers will have access to a stimulating research environment at Ghent University and within the ExaScience Lab. There will be a close collaboration with other Intel labs in Europe and the US.

Employment details:

? Duration: One year, renewable after positive evaluation.

? Application closing date: Positions will be filled as soon as possible.

? Ghent University is committed to equality of opportunity.

An application should include:

? A cover letter expressing the applicant?s research background,

including a clear indication of the level of expertise in the areas mentioned in the job description above;

? A curriculum vitae detailing contact information, degrees obtained

and major research achievements, publication list;

? The names of three contact persons willing to provide a

recommendation letter;

? A statement of availability.

Please send applications to Lieven Eeckhout (Lieven.Eeckhout@UGent.be).

For more information about Lieven Eeckhout?s research activities, please visit http://www.elis.ugent.be/~leeckhou/.

For more information about the ExaScience Lab, please visit http://www.exascience.com/.

POST-DOC position in COMPUTER ARCHITECTURE at UNIVERSITY OF SIENA, ITALY DEADLINE July 29th, 2010 – (OPENING beginning of July) ………………………………………………………………

The DEPARTMENT OF INFORMATION ENGINEERING (UNIVERSITY OF SIENA, ITALY) is pleased to announce the availability of 1 postdoc position in the framework the EUROPEAN RESEARCH (FP7): MULTICORE ARCHITECTURE http://www.teraflux.eu

We are looking for motivated, talented candidates for a post-doc research position in COMPUTER ARCHITECTURE. Specifically, the research topics are closely related to MULTICORE SYSTEMS.

………………………………………………………………

REQUESTED EXPERTISE (MOSTLY COMPUTER ARCHITECTURE) The required profile includes a background/interest in COMPUTER ARCHITECTURE and a good knowledge of written and oral English.

The following expertise is especially considered:

- experience in multicore systems

- experience in performance evaluation

- experience in system simulation

- experience in virtual machine based simulation and modeling

- experience in programming in C and C++

- experience in Linux/Windows internals

- experience in working independently AND in team

- publications in IEEE/ACM Journals or conferences

………………………………………………………………

MORE DETAILS ABOUT THE ERA RESEARCH PROJECT http://www.teraflux.eu Please contact the project coordinator if you need more information.

Roberto Giorgi giorgi@dii.unisi.it

………………………………………………………………

APPLICATION

This research position is open to citizens of any nationality.

However, the application should be prepared in Italian: if you need some assistance for this, please contact Gabriele Cecchetti (gabriele.cecchetti@dii.unisi.it ), who is supervising the application process.

Updates and news on how to apply to this call will be available at:

http://teraflux.eu/PostDocAtUNISI-Call

*** PLEASE NOTE THE APPLICATION DEADLINE IS JULY 29th, 2010 ***

………………………………………………………………

DURATION AND SALARY

Currently, we have 1 available position that can extend up to 3 and half years with a yearly salary of 30keuro **NET**.

The research activity can start almost immediately after the completion of the selection process (01 September 2010).

………………………………………………………………

MORE INFO ABOUT THE UNIVERSITY OF SIENA

- We are part of the HiPEAC NETWORK OF EXCELLENCE and coordinating the TERAFLUX project:

http://www.hipeac.net – http://www.teraflux.eu

- UNIVERSITY OF SIENA: http://www.unisi.it Student services: http://www.unisi.it/v0/pagina_en.htm?fld=2880

- DEPARTMENT OF INFORMATION ENGINEERING: http://www.dii.unisi.it Our Faculty ranks the highest score in Italy for Industrial and Information Engineering (Independent Valuation from the Ministry of University and Research – CIVR 2006)

- ABOUT SIENA: http://en.wikipedia.org/wiki/Siena

A description by Prof. Cetin K. Koc, UCSB:

"To me, the best city in the best region of the world."

- FOR ANY FURTHER INFORMATION

Please contact: Gabriele Cecchetti ( gabriele.cecchetti@dii.unisi.it )

We are advertising two three-year postdoc research positions to work in my group here at Imperial College London, on two linked projects aiming to support abstraction and performance portability in computational science applications targetting parallel, multicore and manycore/GPGPU platforms.

Further details are available at:

http://www3.imperial.ac.uk/computing/situations-vacant#2

"Multilayer Abstractions for Partial Differential Equations on Multicore and Manycore Systems"

and

http://www3.imperial.ac.uk/computing/situations-vacant#3

"Sustainable domain-specific software generation tools for extremely parallel particle-based simulations"

This is an opportunity to take a leadership role in an ambitious multidisciplinary collaboration, involving several exciting applications

- including, for example, ocean circulation modelling, ab initio chemistry, bone implant biomechanics, urban pollution modelling, aeroengine turbomachinery, and dam stability. Applications are of interest both from compiler specialists and from applicants with a numerical methods/HPC background.

Background on the research group is available at http://spo.doc.ic.ac.uk/ and http://www.doc.ic.ac.uk/~phjk/ . Please email Paul Kelly (p.kelly@imperial.ac.uk) to find out more. The deadline for applications is July 1st 2010.

Eindhoven University of Technology

Faculty of Electrical Engineering

Eindhoven

The Netherlands

FTE 1.0

Application Deadline: 31-03-2010

Vacancy Number: V36.1075

The Faculty of Electrical Engineering delivers education and performs scientific and technological research in the broad discipline of Electrical Engineering. Electrical Engineering covers the application of electrical phenomena with respect to energy, information processing and telecommunication, as well as, electrical and electronic components, and the technology involved. Both hardware, in the form of electronic circuits and accessories, and software, in the form of system software for electro-technical applications, are the subject of study. Existing or new electrical devices, components and systems are analyzed, designed, implemented, controlled and realized. In addition, the maintenance of these systems is the subject of research, as is the societal relevance of electrical engineering and information technology.

Position

The position is in the Section of Digital Circuits and Formal Design Methods (DCFDM) of the Electronic Systems (ES) Group. The mission of the ES Group is to provide a scientific basis for design trajectories of digital electronic circuits and systems ‘from (generalized) algorithm to realization’. To identify the key problems, and verify the validity, robustness and completeness of our results, we develop, implement and maintain consistent and complete flows, and use them for realizing innovative hardware, with emphasis on video processing and embedded architectures. The mission of the DCFDM Section is research and development of theory, methods and EDA tools for modeling, analysis, synthesis and optimization of digital circuits and systems to adequately cope with the increasing complexity and challenges of the nano-electronic technologies. It has an internationally recognized expertise in design theory, methodology and electronic design automation for embedded system design and hardware synthesis. It has also experience with FPGA-based design, (re-)configurable architectures, multi-objective circuit and system optimization and automatic architecture synthesis for (heterogeneous) platform-based systems.

Project

The research work will be performed in the scope of the Architecture Synthesis and Application Mapping (ASAM) project, being a part of the European research program ARTEMIS. The ASAM project addresses the problem of an automatic coherent architecture synthesis and application mapping for heterogeneous multi-processor embedded systems based on configurable application-specific instruction-set processors (ASIPs). It aims at defining a new unified design methodology, as well as, related synthesis and prototyping tool-chains for: multi-objective design space exploration for configurable heterogeneous multi-ASIP systems and identification of the application-tailored system architectures; automatic architecture instantiation or customization of particular application-tailored processors, memories and communication structures of the system architecture; optimal hardware synthesis of the created platform; automatic application mapping on the resulting multi-processor heterogeneous platform; and software compiler retargeting and automatic software compilation, all when accounting for the platform hardware characteristics and for the functional and extra-functional requirements and trade-offs.

The research work will be focused on the automatic architecture instantiation or customization of the application-tailored ASIPs, including their extension with new application-specific instructions and related hardware, optimal synthesis of the ASIPs’ hardware, and collaboration of these micro-architecture and hardware synthesis tasks with the memory and communication architecture synthesis, as well as, with the macro-architecture synthesis of the whole heterogeneous multi-processor system.

Tasks

The main tasks include:

• research work in the scope of the above described project involving development of new design methods, and related electronic design automation (EDA) analysis and synthesis flows and tools, software implementation of the prototype EDA tools and flows, and experimental research with their use;
• assistance to the project coordinator in implementation of the coordination decisions, as well as, coordination, organization, communication and reporting activities, and in supervision of the junior researchers and students;
• establishing and adequately running of the project web-page.

Requirements

Candidates for this Post-doc researcher position should meet the following requirements:

• MSc in Embedded Systems, Computer Engineering, Electronics, Electrical Engineering, Information Technology or related area, with an advanced knowledge or minor/majors in subjects related to electronic design automation, (embedded) processor architectures and/or SoC design;
• Ph.D. degree preferably or P.D. Eng. Degree and an equivalent amount of experience, or MSc degree and a proven large amount of experience and substantial achievements in research and development related to electronic design automation, (embedded) processor architectures and/or SoC design;
• a solid knowledge of and substantial experience in software design and programming, including knowledge of and experience with programming in C++ and/or C;
• excellent invention and learning abilities;
• excellent analytical, organizational and communication skills, including an ability of effective and efficient individual work, as well as, easy cooperation in a team with supervisors, students, other researchers and companies, and excellent English language capabilities both in writing and speaking;
• a substantial knowledge of or experience with ASIP processors, instruction-set synthesis, (re-)configurable systems, FPGA-based design and prototyping, and related EDA tools will be a premium.

Appointment and Salary

The appointment is of immediately and can start as soon as possible. The appointment will be for three years. The gross monthly salary will be in accordance with the Collective Labor agreement of the Dutch Universities (CAO NU) and amounts to at least € 2861 per month (initially, scale 10.4) depending on prior experience. An offer will be based on your knowledge and experience. An attractive package of fringe benefits (including excellent work facilities, end of the year allowance and sport facilities). Moreover an 8% bonus share (holiday supplement) is provided annually.

Information

For more information on the project, tasks or requirements please contact Dr. ir. L. Józwiak, tel. +31-(0)40-2473645, e-mail: L.Jozwiak@tue.nl.

For terms on employment please contact: Mr. P.F.M. Tiel Groenestege, HR advisor of the Faculty of Electrical Engineering tel. +31-(0)40-2472004, e-mail: p.f.m.tiel.groenestege@tue.nl .

More information and on-line application form can be found on the TU/e web-pages:

http://jobs.tue.nl/wd/plsql/wd_portal.search_results?p_web_site_id=3085&p_category_id=3713&p_show_results=Y&p_form_type=CHECKBOX&p_no_days=999&p1=6047&p1_val=Any&p2=6048&p2_val=Department+of+Electrical+Engineering&p_text=&p_save_search=N

and

http://w3.tue.nl/en/services/dpo/excellent_jobs_for_excellent_people

Title of the proposal: Efficient Resource Utilization in Dynamically Reconfigurable Multi-processor Embedded Systems

Keywords: Reconfigurable (FPGA) Systems, Partial and dynamic reconfiguration, programming/execution model, Multi-cores, Embedded architectures, energy/power consumption saving.

Author of the proposal: Jean-Luc Dekeyser, Smail Niar, Samy Meftali

Supervisor of the Post-doc: Jean-Luc Dekeyser, Smail Niar, Samy Meftali

Team-Project: DART

Location: LILLE

Scientific context:

The computing industry is trying to improve embedded system performances with parallel execution and reconfigurability[1][2]. If the trend towards the use of multi-cores systems does not need to demonstrate, the use of reconfigurable circuits (RC) is much more recent. This solution represents an alternative to GPPs and ASICs as it offers a good compromise between the GPP flexibility and ASICs performances. Thanks to the technological evolution, the number of logical cells has strongly augmented. The recent Virtex6 Xilinx FPGA family for instance contains 6 times more logical elements and DSPs than the VirtexII family [3] designed 6 years ago, all with a 60% power consumption reduction. According to the ITRS [2] this tendency will grow in the coming years. It will be then possible over the years to put on a RC, hundreds of processors with their interconnection network [4][5].

Another benefit in the use of RCs is their ability to offer partially and dynamic reconfiguration. In the area of MPSoC, this feature can be used to add specialized computing cores on the FPGAs function of the application parameters and running conditions. FPGA flexibility thus allows programmers to reconfigure them as needed. Consequently, multiple low-frequency heterogeneous cores and IPs can be used to provide further power savings by specialization. As a result, customized programmable hardware can significantly improve the execution speed with lower energy budget [6][7].

Goal:

In spite of these achievements, programming and efficient exploitation of these dynamically RC remains a painful and complicated task.

For instance in the past the vast majority of FPGA users were hardware designers with an important amount of knowledge and experience in circuit design. VHDL or Verilog are the most used languages to program these FPGA. These languages are however unfamiliar to the majority of SoC software programmers. In addition, the management of partially dynamically reconfigurable circuits with the existing tools does not allow an efficient and an easy use of the huge FPGA possibilities.

The objective of this post-doc is to collaborate in designing a methodology for a better and easy utilization of current and future FPGA hardware resources. The post doctor must lead to the proposal of a new programming and execution model specific to multi-processor architecture systems on FPGA. Heterogeneity and dynamic reconfigurability are the main features that must be taken into account.

To allow an efficient and dynamic control of the system resources, the model must define new services either at the operating system level or at the hardware level (performance monitoring unit). Through these services, it will be possible for the developer to determine at run time the state of the system and the application needs. This may correspond to application energy consumption, cache or memory activities, and workload at the NoC level, etc. On the other side, and by the using of this information, the application developer will be able to control the dynamic application deployment on the architecture.

Required skills:

Candidates must have (or are about to receive) a Ph.D. in the domain of Embedded Sw or Hw design. He/She must have a strong background either in parallel programming models or in reconfigurable embedded system design.

To apply, please visit:

http://www.inria.fr/travailler/mrted/en/postdoc/details.html?id=PNGFK026203F3VBQB6G68LOE1&LOV5=4508&LG=EN&Resultsperpage=20&nPostingID=3860&nPostingTargetID=8353&option=29&sort=ASC&nDepartmentID=19

Bilbiographical References:

1.     1 M.Duranton and Al., Hipeac roadmap, 2009

http://www.hipeac.net/system/files/lr_3128_hipeac_roadmap-2009-v5.pdf

2.     2 www.itrs.com

3.   3   www.xilinx.com

4.    4  www.eve.com

5. 5 X.Li and O.Hammami, Fast Design Productivity for Embedded Multiprocessor through Multi-FPGA Emulation: The case of a 48-way Multiprocessor with NOC.

6. 6 R. Wain et Al., An overview of FPGAs and FPGA programming, internal technical report, CCLRC Daresbury Laboratory, 2006.

7. 7 A.Donlin, Applications, Design Tools and Low Power Issues in FPGA Reconfiguration, in “Designing Embedded Processors” book.

8. 8 V.M. Sima , K. Bertels, Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform, 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS’09).

A postdoctoral position is available at the High Performance Computing Architecture and Technologies (HPCAT) Lab at the Department of Electrical and Computer Engineering, University of Arizona, Tucson. The position is available immediately.

The research focus for this position is on the development and design of network-on-chips (NoCs) for multi-core architectures with particular focus on analysis of power- performance trade-offs, design of fault-tolerant circuits router architecture optimizations, and utilization of  emerging technologies (e.g. optical interconnects, wireless, 3D).

Applicants should have earned a PhD degree in Electrical Engineering, Computer Engineering, or Computer Science and Engineering. Experience in computer architecture, interconnection networks, multi-core designs, and reliable computing is highly desirable.

Please submit, by email, a single attachment, that includes your CV, a brief statement of your research accomplishments and interests, a sample of a publication, and the contact information for three references, to:

Prof. Ahmed Louri

Director, HPCAT

Department of Electrical and Computer Engineering University of Arizona Tucson, AZ 85721

Tel: 520-621-2318

Fax: 520-621-8076

E-mail: vtbhat@email.arizona.edu

This position spans two projects studying ways to balance high performance and power efficiency in both software and hardware. On the software side, we are developing on-line power estimation and performance models to drive power-aware, intelligent software resource managers on server-class machines and embedded DSP chip multiprocessors. On the hardware side, we are studying power-efficient adaptable architectures.

Excellent communication skills (both in speaking and writing) in English are essential. Leadership skills are also necessary.

The ability to identify important problems, formulate a research agenda, and carry out that agenda independently or in close collaboration with others is important.

Please see the below URL for more information and instructions on how to apply:

http://www.chalmers.se/cse/EN/news/vacancies/positions/postdoctoral-position-in

All applications must be electronic.

Email Sally McKee (mckee@chalmers.se) with any questions.

The Institute of Computer Science at the University of Innsbruck, Austria, invites applications for a Postdoc position with the opportunity for habilitation in the field of "parallel processing" in the Distributed and Parallel Systems Group (DPS).

This is a 4 year university position which can be extended based on an evaluation at the end of the 4 year period.

Your areas of interest should comprise:

· Application development and runtime environments for multi-core parallel architectures

· Program analysis and optimizations for parallel systems

· Programming languages and methods for multiprocessor architectures

· Performance analysis and debugging for parallel programs

Prerequisites:

Applicants must hold a doctoral degree in computer science and require a working permit for the European Union.

Profile of our group:

DPS participated among others in the following projects:

EU Apart working group, EU CoreGRID, EU EC-GIN, EU edutain@grid, EU Adaptive Services Grid, EU K-WF Grid, EU EGEE 1-3, EU Coregrid, EU HiPEAC, SFB Aurora and Austrian Grid.

Language Skills:

The working and study language is English. The entire course and research programme is held in English only. There is no need to learn German for this position Innsbruck and its Environment:

The City of Innsbruck, which hosted the Olympic winter games twice, is located in the beautiful surroundings of the Tyrolean Alps. The combination of the Alpine environment and the urban life in this historically grown town provides a high quality of living. The university has a long tradition dating back to the 16th century, and, with seven schools (Theology, Law, Economics and Social Sciences, Medicine, Humanities, Natural Sciences, Civil Engineering and Architecture), it offers a wide spectrum of research and teaching activities and interesting opportunities for interdisciplinary collaboration.

Besides, the Country of Tyrol strongly supports various initiatives in the IT domain.

Applications must be submitted before Nov. 30, 2009. Please direct questions and your application to:

Prof. Dr. Thomas Fahringer

Institute of Computer Science, University of Innsbruck Technikerstr. 21a, A-6020 Innsbruck, Austria

Email: Thomas.Fahringer@uibk.ac.at

URL: dps.uibk.ac.at

……………………………………………………….

The DEPARTMENT OF INFORMATION ENGINEERING (UNIVERSITY OF SIENA, ITALY) is pleased to announce the availability of several Research Opportunities in the framework of EUROPEAN RESEARCH (FP7).

We are looking for motivated, talented candidates for several different research positions in COMPUTER ARCHITECTURE: Engineer, PhD student, Post-Doc, Research Assistant.

……………………………………………………….

EXPERTISE

The required profile includes a background/interest in COMPUTER ARCHITECTURE and a good knowledge of written and oral English.

The following expertise is especially considered:

- experience in system simulation

- experience in programming in major languages (C, C++, Java)

- experience in Linux/Windows internals

- experience in working independently AND in team

……………………………………………………….

DURATION AND SALARY

We offer positions that can extend up to 4 years with salaries reaching highest levels according to the candidate experience.

……………………………………………………….

COMPUTER ARCHITECTURE TOPICS

The list of topics includes (but it is not limited to):

- future multicore architectures (10^12 devices)

- reconfigurable architectures for embedded systems

- virtual machine based simulation and modeling

- application and operating system self-adaption ……………………………………………………….

PHD APPLICANTS:

PLEASE NOTE THE CLOSE DEADLINE (24th JULY 2009).

We expecially consider candidates from abroad Italy (and inside Italy) and we will cover travel expenses and health insurance for candidates who are successfully admitted to the PhD program.

Besides regular salary, our students will be considered for a special yearly productivity prize based on publication record (an extra 5000 euro).

The application requires the following steps:

1) a pre-registration at the site:

http://dottorati.unisi.it/domande/domandaXXV_sd_giugno.asp?ID=515

2) Include an abstract (1-2 pages) of a research project in Computer Architecture to be agreed with the adviser (please send email to:

giorgi@dii.unisi.it AND bartolini@dii.unisi.it ) on the above topics.

3) fill in and post the application form

http://dottorati.unisi.it/domande/application_form_09_giugno.doc

together with the research project abstract

Our PhD school is part of the ITALIAN EXCELLENCE CENTER "Superior School Santa Chiara" http://www.unisi.it/santachiara/ Candidates are welcome to apply for a hosting in this facility which is 100 meters from our Faculty.

………………………………………………………..

ENGINEER, POSTDOC/RESEARCH ASSOCIATE, RESEARCH ASSISTANT CANDIDATES:

Please send in your CV possibly before September 15th, 2009 to giorgi@dii.unisi.it

………………………………………………………..

MORE INFO:

- We are part of the HiPEAC NETWORK OF EXCELLENCE

http://www.hipeac.net

- UNIVERSITY OF SIENA: http://www.unisi.it

Student services: http://www.unisi.it/v0/pagina_en.htm?fld=2880

- DEPARTMENT OF INFORMATION ENGINEERING: http://www.dii.unisi.it

Our Faculty ranks the highest score in Italy for

Industrial and Information Engineering (Independent Valuation from

the Ministry of University and Research – CIVR 2006)

- ABOUT SIENA: http://en.wikipedia.org/wiki/Siena

A description by Prof. Cetin K. Koc, UCSB:

"To me, the best city in the best region of the world."

- FOR ANY FURTHER INFORMATION

Please contact prof. Roberto Giorgi giorgi@dii.unisi.it