Call for Papers

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Call for Papers
SPEC 2009
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January 25, 2009
Austin, Texas
www.spec.org/workshops/2009/austin/

The goal of the SPEC 2009 Workshop is to provide a forum for academia and industry to discuss the practice of system performance evaluation by the sharing of ideas and experiences. The workshop will bring together developers and users of performance evaluation software and will be held on Sunday, January 25, 2009 in Austin, Texas, in conjunction with SPEC\’s Annual meeting.

Presentations will center on novel performance evaluation strategies; new benchmark design; use of benchmarks in industry, academia and government; and workload characterization. While traditional areas of performance evaluation are solicited, papers addressing the emerging areas related to evaluating power, reliability, virtualization scalability and security are also of interest.

Standard Performance Evaluation Corporation, (SPEC) invites the performance evaluation community to submit full papers and extended abstracts on a range of topics relevant to performance evaluation. The proceedings will be published by Springer-Verlag (pending approval).

Submission guidelines:
Full (20 page) and short (8 page) papers are solicited. Submissions should be formatted according to the LNCS format (see author\’s instructions given on www.springer.de/comp/lncs/authors.html).
Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this workshop. Papers must be submitted electronically in PDF format.

Important Dates:
Paper/extended abstract Submission: October 3, 2008
Notification of Acceptances: October 26, 2008
Final Version of Papers: November 9, 2009
Workshop: January 25, 2009

General Chair: Rudi Eigenmann Purdue University
Program Chair: David Kaeli Northeastern University
Publication Chair: Kai Sachs TU Darmstadt

Program Committee
Jose Nelson Amaral – University of Alberta
Umesh Bellur – Indian Institute of Technology Bombay
Tom Conte – Georgia Tech
Anton Chernoff – AMD
Lieven Eeckhout – University of Ghent
Rudi Eigenmann – Purdue University
Jose Gonzalez – Intel Barcelona
John Henning – Sun Microsystems
Lizy John – University of Texas at Austin
David Kaeli – Northeastern University
Helen Karatza – Aristotle University of Thessaloniki
Samuel Kounev – Universitt Karlsruhe (TH)
Tao Li – University of Florida
David Lilja – University of Minnesota
Christoph Lindemann – University of Leipzig
John Mashey – Consultant
Jeffrey Reilly – Intel
Resit Sendag – University of Rhode Island
Erich Strohmaier – Lawrence Berkeley National Labs
Bronis Supinski – Lawrence Livermore National Labs
Petr Tuma – Charles University in Prague

Steering Committee:
Alan Adamson – IBM Canada
Jose Nelson Amaral – University of Alberta
David Bader – Georgia Tech
Rudi Eigenmann – Purdue University
Rema Hariharan – AMD
John Henning – Sun Microsystems
Lizy John – University of Texas at Austin
David Kaeli – Northeastern University
Samuel Kounev – Universitt Karlsruhe (TH)
David Morse – Dell
Kai Sachs – TU Darmstadt

Held in Cooperation with:

IEEE Technical Committee on Computer Architecture (TCCA)

International Symposium on Performance Analysis of Systems and Software
ISPASS-2009
Boston, MA
April 19-21, 2009

Sponsored by the IEEE Computer Society?s TCI, TCCA, and TC-uARCH

The IEEE International Symposium on Performance Analysis of Systems and Software provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software.
Authors are invited to submit previously unpublished work for possible presentation at the conference.

Papers are solicited in fields that include the following:

* Performance evaluation methodologies
o Analytical modeling
o Statistical approaches
o Tracing and profiling tools
o Simulation techniques
o Hardware (e.g., FPGA) accelerated simulation
o Hardware performance counter architectures
* Performance analysis
o Performance metrics
o Bottleneck identification and analysis
o Visualization
* Performance analysis of commercial and experimental hardware
o General-purpose microprocessors
o Multi-threaded, multi-core and many-core architectures
o Accelerators and graphics processing units
o Embedded and mobile systems
o Enterprise systems and data centers
o Supercomputers
o Computer networks
* Performance analysis of emerging workloads and software
o Software written in managed languages
o Virtualization and consolidation workloads
o Internet-sector workloads
o Embedded, multimedia, games, telepresence
o Bioinformatics, life sciences, security, biometrics
* Application and system code tuning and optimization
* Confirmations or refutations of important prior results

Next to *research papers*, we also welcome *tool papers* in order to reward tool-building effort and publicize new tools to the community. Tool papers will be judged more so on their potentially wide impact and use than on their research contribution. Tools in any of the above fields of interest are eligible.

See www.ispass.org for submission details.

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IMPORTANT DATES

Abstract due: Oct 3, 2008
Full submission: Oct 10, 2008 ? NO EXTENSION
Rebuttal: Dec 4-5, 2008
Notification: Dec 17, 2008
Final paper due: Feb 25, 2009

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ORGANIZING COMMITTEE

GENERAL CHAIRS
Dean Tullsen, UC San Diego
Todd Austin, University of Michigan

PROGRAM CHAIR
Lieven Eeckhout, Ghent University

PROGRAM COMMITTEE
Tor Aamodt, University of British Columbia
Steve Blackburn, Australian National University
Pradip Bose, IBM Research
David Brooks, Harvard University
Derek Chiou, University of Texas at Austin
Bronis R. de Supinski, LLNL
Sudhanva Gurumurthi, University of Virginia
Greg Hamerly, Baylor University
Ravishankar Iyer, Intel
Aamer Jaleel, Intel
Stefanos Kaxiras, University of Patras
Rakesh Kumar, UIUC
Benjamin Lee, Microsoft Research
Charles Lefurgy, IBM
Mikko Lipasti, University of Wisconsin?Madison
Daniel Ortega, HP Labs
Steve Reinhardt, AMD
Scott Rixner, Rice University
Eric Rotenberg, NCSU
Andr=E9 Seznec, IRISA
Tim Sherwood, UC Santa Barbara
Allen Snavely, UC San Diego
Thomas Wenisch, University of Michigan

LOCAL ARRANGEMENTS CHAIR
TBD

PUBLICITY CHAIR
Elmoustapha Ould-Ahmed-Vall, Intel

FINANCE CHAIR
Nadeem Malik, IBM

WEB CHAIR
Byeong Kil Lee, TI

PUBLICATIONS CHAIR
Rakesh Kumar, UIUC

WORKSHOPS/TUTORIALS CHAIR
Jun Yang, University of Pittsburgh

REGISTRATION CHAIR
Rajeev Balasubramonian, University of Utah

SUBMISSION AND REVIEW WEB CHAIR
Michiel Ronsse, Ghent University

* With apologies for cross-posting: *
* Post-doctoral position in Model-Driven Engineering (MDE) *
* for Multi-Processor Systems-on-Chip (MP-SoC) *

The Software Engineering Group of the University of Antwerp (Belgium, www.ua.ac.be/) seeks candidates for a post-doctoral position in the area of model-driven software engineering for embedded systems.
The group currently consists of 2 senior staff, 2 postdoc researchers and 8 PhD students, and is expanding. The selected candidate will be involved in the OptiMMA (Optimized MP-SoC Middleware for Event-driven Applications) project that aims at improving the design and performance of middleware components for concurrent systems-on-chip:
See www.imec.be/OptiMMA/.

The project involves several universities as well as IMEC, a leading research institute for microelectronics and design methods for ICT systems.

We are looking for candidates interested in model-based software engineering, modeling languages (UML and others), model transformation tools, and their application to the development of middleware components for embedded systems. Ideally the candidate should start on november 1, 2008, or before. The project runs until december 31, 2011. Candidates for the position should have a doctoral degree in software engineering or a closely related field and research experience in the topics mentioned.

We offer a gross salary of between 3500=80 and 4000=80 per month.

Interested candidates can send an application by email including a motivation letter, C.V., list of publications and 2 academic references to the following address. More information, about the project or otherwise, can also be obtained from there.

Dirk Janssens (Dirk.Janssens at ua.ac.be)
Dept of Mathematics and Computer Science
University of Antwerp
Middelheimlaan 1,
2020 Antwerp,
Belgium

—————————————————————————— LAGrid08 – 2n Intl. Latin American Grid Workshop lagrid08.lncc.br —————————————————————————— in conjunction with 20th Intl. Symposium on Computer Architecture and High Performance Computing Campo Grande – Brazil October 29th – November 1st, 2008 —————————————————-
The goal of the Latin American Grid (LAGrid) workshop is to act as a forum for technical presentations of ongoing research, development and relevant activities in the area of Grid Infrastructures, Services and Applications, in the context of and/or in partnership with Latin America.
The event focuses on bringing together researchers and professionals actively working in this field, promoting multi-institutional collaborations between groups of diverse competences.

The LAGrid workshop gives particular attention to the Grid deployment initiatives in Latin America and the challenges they face as regards the distribution of and efficient access to scarce compute, storage and communication resources in this continent. Discussions and studies about new application areas and the potential impact of Grid technology in Latin America are also of main interest.

Authors are therefore particularly encouraged to submit reports about their experiences in deploying Grid Infrastructures, Services and Applications.
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Selected papers will be invited to submit extended versions to a Special Issue of Concurrency and Computation: Practice and Experience Journal.
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Deadlines
====================================================
Submisssion: September 1st – 2008
Communication to Authors: September 29th – 2008
Camera Ready: October 14th – 2008
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The areas of interest in LAGrid 2008 include, but are not limited to: ==================================================== * Cyberinfrastructures in Latin America; * Impact of Grid technology in Latin America;
* Applications for Latin America;
* Middleware solutions for Latin America;
* Promoting e-Science collaborations in Latin America;
* Funding models supporting Latin America cyberinfrastructures;
* Cost-effective solutions for Latin America;
* Grid economy models for Latin America;
* Role of Grids in broadening participation in science and education in
Latin America.
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Submission Format
====================================================
Authors should submit papers of no more than 6 pages in a two-column format.
The main text must be in 10-point Times, single-spaced. For further information refer to the author guidelines for IEEE CS 8.5 x 11-inch proceedings manuscripts. Authors should submit a PostScript (level 2) or PDF file that will print on a PostScript printer. Submission implies the willingness of at least one of the authors to register to the conference and workshop and present the paper. Submitted papers will be reviewed by at least 3 reviewers. Submission is electronic only at submissoes.sbc.org.br/Paper.cgi?c=717&track=1792 .
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Workshop Chairs:
Bruno Schulze – LNCC, BR
Francisco Brasileiro – UFCG, BR
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CALL FOR PAPERS

Second Workshop on Programmability Issues for Multi-Core Computers
(MULTIPROG-2009)

Held in conjunction with the 4th International Conference on
High-Performance

and Embedded Architectures and Compilers (HiPEAC)

Paphos, Cyprus, January 25-28, 2009

Goal of the Workshop

——————–

Computer manufacturers have already embarked on the multi-core roadmap, promising
to double the number of processors on a chip every other year, and many-cores are
on the horizon. This shift to an increasing number of cores has placed new burdens
on the programming community. Until now, software has been developed with a single
processor in mind and it needs to be parallelized to take advantage of the new
breed of multi-/many-core computers. As a result, progress in how to easily harness
the computing power of multi-core architectures is in great demand.

This workshop aims to bring together, and cause fruitful interaction between,
researchers interested in programming models and their implementation and in

computer architecture with the common interest in advancing our knowledge how to
simplify the task of parallelization of software for multi-core platforms. A wide
spectrum of issues are central themes for this workshop such as what the future
programming models should look like to accelerate software productivity and how
it should be implemented at the runtime, the compiler, and the architecture level.

We will prioritize papers reporting on on-going work that address cross-cutting
issues and that provide thought-provoking insights into the main themes.
Proceedings

with accepted papers will be made available at the workshop. Selected papers will
appear on a special issue of Transactions on HiPEAC, after a new review process.

Topics of interest

——————

Papers are sought on topics including, but not limited to:

* Multi-core architectures

o Architectural support for compilers/programming models
o Processor (core) architecture and accelerators (GPUs, …)
o Memory system architecture

o Performance/power issues

* Programming models for multi-core architectures

o Language extensions

o Run-time systems

o Compiler optimizations and techniques

o Tools for discovering and understanding parallelism
* Applications for multi-core architectures

o Methodologies for developing applications

o Benchmarking

Organizers

———-

Eduard Ayguade Barcelona Supercomputing Center Spain (eduard[at] ac.upc.edu)
Roberto Gioiosa Barcelona Supercomputing Center Spain
(roberto.gioiosa[at]bsc.es)

Per Stenstrom Chalmers University of Technology Sweden (pers[at] chalmers.se)
Osman Unsal Barcelona Supercomputing Center Spain
(osman.unsal[at]bsc.es)

Important dates

—————

Submission deadline: Oct 10, 2008

Notification to authors: Nov 28, 2008

Final version of accepted papers: Dec 19, 2008

Paper submission

—————-

Submitted papers should use the LNCS format and should be 12 pages maximum.
Manuscript

preparation guidelines can be found at the LNCS web site (
www.springeronline.com/lncs,

go to -> For Authors -> Information for LNCS Authors). Submit your paper through the
MULTIPROG submission server (multiprog.ac.upc.edu/CRP/).

Program Committee

—————-

TBD

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Call for Papers: NoCArc 2008
First International Workshop on Network on Chip Architectures To be held in conjunction with the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41) 8th November, 2008 Lake Como, Italy ==========================
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=======================

General Information
——————-
Single chip embedded systems are becoming increasingly complex and heterogeneous. Such Systems-on-Chip (SoCs) require seamless integration of numerous IP cores performing different functions and operating at different clock frequencies. Network-on-Chip (NoC) is generally viewed as the ultimate solution for the design of modular and scalable communication architectures and provides inherent support to the integration of heterogeneous cores through the standardization of the network interfaces. This workshop is focused on issues related to design, analysis and testing of on-chip networks.

Areas of Interest
—————–
The topics of specific interest for the workshop include, but are not limited to:
* Architectures and Topologies for NoCs and MPSoCs
* Routing algorithms and Router Micro-architectures
* Fault tolerance, reliability and testing issues
* Dynamic on-chip network reconfiguration
* Modeling and evaluation of on-chip networks
* Design space exploration and tradeoff analysis
* On-chip interconnection network simulators and emulators
* Industrial case studies of SoC designs using the NoC paradigm

The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing \”work in progress\” or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Submission Guidelines
———————

The authors are invited to submit unpublished work related to
workshopss s theme. Both research and application-oriented papers are welcome. All papers should be submitted electronically via the workshop web-page at:
www.diit.unict.it/users/mpalesi/nocarc/.

Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Papers should be formatted in accordance with the templates published in the workshop webpage (standard double-column IEEE in A4 format). Submissions must be limited to 6 pages. If the authors wish a blind review to be performed, then the author\’s name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.

Important Dates
—————
Submission deadline 24th August, 2008
Author notification 1st October, 2008
Camera-ready version due 10th October, 2008
NoCArc Workshop 8th November, 2008

Workshop Organizers
——————-
* Maurizio Palesi
Dipartimento di Ingegneria Informatica e delle Telecomunicazioni University of Catania, Italy www.diit.unict.it/users/mpalesi
* Shashi Kumar
Department of Electronics and Computer Engineering
School of Engineering
J=F6nk=F6ping University, Sweden
hem.hj.se/~kush/

Program Committee
—————–
* Federico Angiolini, iNoCs, Switzerland
* Davide Bertozzi, University of Ferrara, Italy
* Giorgos Dimitrakopoulos, FORTH, Greece
* Jos=E9 Flich Cardo, Universidad Polit=E9cnica de Valencia, Spain
* Ahmed Hemani, Royal Institute of Technology, Sweden
* Anshul Kumar, Indian Institute of Technology, India
* Marcello Lajolo, NEC Laboratories America, NJ, USA
* Zhonghai Lu, Royal Institute of Technology, Sweden
* Srinivasan Murali, EPFL, Switzerland and Stanford University, USA
* Juan Manuel Ordu=F1a Huertas, Universidad de Valencia, Spain
* Davide Patti, University of Catania, Italy
* Partha P. Pande, Washington State University, USA
* Timothy M. Pinkston, University of Southern California, USA
* Carlo Pistritto, STMicroelectronics, Italy
* Tor Skeie, University of Oslo, Norway
* Vittorio Zaccaria, Politecnico di Milano, Italy

Multiple positions in Intel Oregon Computer Architecture team
==========================
==========================
===========

The Intel Oregon Computer Architecture team (ORCA) develops leading-edge IA32 processors; the current Nehalem processor is the latest processor designed by ORCA, but the group has members who were involved with the design of the Pentium and the Pentium Pro/Pentium II (if not earlier) processors as well.

The areas that we=B9re hiring for include:

Core Microarchitecture/Performance Modeling
Software/Tools Development
Microcode Development
Power Management

The group is based out of Hillsboro, Oregon, just West of Portland, Oregon.
Seattle, Washington is three hours to the North and Vancouver, B.C., Canada is a couple of hours further up the highway. The Pacific Northwest (including Oregon, Washington, and British Columbia) has great outdoor activities during all seasons: easily within at most a few hours drive fro= m Portland there is bicycling, skiing, hiking, climbing, mountaineering, fishing, surfing, SCUBA diving, boating, paddling, rowing, and so forth.
Portland also has a great art and culture scene including museums and a wid= e range of stage and music venues.

SALARY
——-
Salary is dependent on background and experience. All levels (BS, MS, PhD; recent graduate and experienced) are encouraged to apply.

CONTACT and DEADLINE
——————–
There is no deadline for application but positions will be filled as qualified candidates are found.

Enquiries/resum=E9s may be sent to:

Dr. Kevin W. Rudd, kevin.w.rudd@intel.com

==========================
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=======================
Call for Papers: HipHaC\’08
First International Workshop on
New Frontiers in High-performance and Hardware-aware Computing To be held in conjunction with the 41st Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-41) November 8, 2008 Lake Como, Italy ========== ==========================
==========================
==============

General Information
——————-

Heterogeneity and reconfigurability in computer systems is growing. Multi- = and manycore-based systems are complemented by coprocessors, accelerators a= nd reconfigurable units providing huge computational power. However, applic= ations of scientific interest (e.g. in high-performance computing and numer= ical simulation) are not yet ready to exploit the available high computing = potential. Different programming models, non-adjusted interfaces, and bandw= idth bottlenecks complicate holistic programming approaches for heterogeneo= us architectures. In modern microprocessors, hierarchical memory layouts an= d complex logics obscure predictability of memory transfers or performance = estimations.

For efficient implementations and optimal results, underlying algorithms an= d mathematical solution methods have to be adapted carefully to architectur= al constraints like fine-grained parallelism and memory or bandwidth limita= tions that require additional communication and synchronization.
Currently, a comprehensive knowledge of underlying hardware is therefore ma= ndatory for application programmers. Hence, there is strong need for virtua= lization concepts that free programmers from hardware details, maintaining = best performance and enable deployment in heterogeneous and reconfigurable = environments.

Possible solutions may consist of supporting libraries, software layers, an= d tools that automatically care for adaptations of program parameters like = block sizes or communication patterns. Autotuning concepts are a possible a= pproach for finding non-obvious optimal choices of such parameters.

This workshop aims at combining new aspects of parallel, heterogeneous, and= reconfigurable microprocessor technologies with concepts of high-performan= ce computing and, particularly, numerical solution methods. Compute- and me= mory-intensive applications can only benefit from the full hardware potenti= al if all features on all levels are taken into account in a holistic appro= ach.

Topics of interest for workshop submissions include (but are not limited to= ): ——————
* Emerging hardware architectures (Multicores, Cell BE, GPUs, FPGAs, …)
* High-performance heterogeneous, adaptive, and reconfigurable
architectures
* Parallelization strategies in hybrid and hierarchical setups
* Hardware-aware computing and code optimization strategies
* Virtualization and software layers for heterogeneous and
reconfigurable platforms freeing programmers from dedicated hardware knowledge * Architecture-aware approaches for parallel numerical applications,
implementation, and algorithm design
* Programming models, compiler techniques, and code optimization
strategies for parallel systems
* Autotuning concepts and run-time adaptivity
* Practice and experience of multicore programming
* Performance evaluation of scientific applications on emerging hardware
* Tools for design, programming, and optimization

Submission guidelines:
———————-
You are invited to submit papers not exceeding 8 double-column IEEE formatt= ed pages (including up to 6 keywords and an abstract of no more than 350 wo= rds), describing original, unpublished recent work related to the workshop = theme. Submission must be in PDF format and emailed to
submission@hiphac.org

If you wish a blind review to be performed, do not include the author\’s nam= e and affiliation in the paper. In case of any questions please contact the= workshop organizers.

The selected papers will be published as printed workshop proceedings throu= gh Karlsruhe University Press.

In case of any questions please contact the workshop organizers.

Important Dates:
—————-
Paper Submission Deadline: September 1, 2008
Notification of Acceptance: September 29, 2008
Camera-ready Papers: October 10, 2008
HipHaC Workshop: November 8, 2008

Organizers
———-
Rainer Buchty, Karlsruhe Institute of Technology, Germany
(rainer.buchty@kit.edu)

Jan-Philipp Wei=DF, Karlsruhe Institute of Technology, Germany
(jan-philipp.weiss@kit.edu)

Steering Committee
——————
J=FCrgen Becker, Karlsruhe Institute of Technology, Germany Vincent Heuveli= ne, Karlsruhe Institute of Technology, Germany Wolfgang Karl, Karlsruhe Ins= titute of Technology, Germany Jan-Philipp Wei=DF, Karlsruhe Institute of Te= chnology, Germany

Program Committee
—————–
J=FCrgen Becker, Karlsruhe Institute of Technology, Germany Mladen Berekovi= c, Univ. Braunschweig, Germany Alan Berenbaum, SMSC, USA Nevin Heintze, Goo= gle Inc.
Vincent Heuveline, Karlsruhe Institute of Technology, Germany Eric D\’Hollan= der, Ghent University, Belgium Ben Juurlink, TU Delft, The Netherlands Paul= Kelly, Imperial College, UK Wolfgang Karl, Karlsruhe Institute of Technolo= gy, Germany Richard Kaufmann, Hewlett-Packard, USA Hsin-Ying Lin, Intel, US= A Scott McClellan, Hewlett-Packard, USA Andy Nisbet, Manchester Metropolita= n University, UK Ulrich R=FCde, Universit=E4t Erlangen-N=FCrnberg, Germany = Martin Schulz, LLNL, USA Thomas Steinke, Zuse-Institut Berlin, Germany Robe= rt Strzodka, Max Planck Institut Informatik, Germany Stephan Wong, TU Delft= , The Netherlands

Electronic Information
———————-
Workshop Flyer with all information:
www.hiphac.org/flyer/

Workshop Website with all information:
www.hiphac.org