Call for Papers

Two positions as Ass. Professor with Tenure Track, Umea University, Sweden

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We seek outstanding candidates for the following new tenure track

positions:

- Assistant Professor in Parallel and Multicore Computing (Dnr 312-489-10)

- Assistant Professor in Industrial and Applied Mathematics (Dnr

312-490-10)

For further information of the positions, please contact professor Bo Kagstrom at the Department of Computing Science and HPC2N

(bokg@cs.umu.se) or professor Mats Larson at the Department of Mathematics and Mathematical Statistcics (mats.larson@math.umu.se).

For the complete announcement, visit:

http://www8.umu.se/umu/aktuellt/arkiv/lediga_tjanster/312-489-490-10.html

We are advertising two three-year postdoc research positions to work in my group here at Imperial College London, on two linked projects aiming to support abstraction and performance portability in computational science applications targetting parallel, multicore and manycore/GPGPU platforms.

Further details are available at:

http://www3.imperial.ac.uk/computing/situations-vacant#2

"Multilayer Abstractions for Partial Differential Equations on Multicore and Manycore Systems"

and

http://www3.imperial.ac.uk/computing/situations-vacant#3

"Sustainable domain-specific software generation tools for extremely parallel particle-based simulations"

This is an opportunity to take a leadership role in an ambitious multidisciplinary collaboration, involving several exciting applications

- including, for example, ocean circulation modelling, ab initio chemistry, bone implant biomechanics, urban pollution modelling, aeroengine turbomachinery, and dam stability. Applications are of interest both from compiler specialists and from applicants with a numerical methods/HPC background.

Background on the research group is available at http://spo.doc.ic.ac.uk/ and http://www.doc.ic.ac.uk/~phjk/ . Please email Paul Kelly (p.kelly@imperial.ac.uk) to find out more. The deadline for applications is July 1st 2010.

We are pleased to announce the availability of funded PhD positions in the Compiler Technology and Computer Architecture group at the University of Hertfordshire. The positions comprise an open studentship and we expect prospective candidates to propose their own line of research within the group’s wide area of interest.

The University of Hertfordshire near London was one of the first academic institutions in the United Kingdom to offer a degree in computer science. Today, the university is the UK’s leading business-facing university with strong industrial ties and an international outreach.

The Compiler Technology and Computer Architecture group is part of the School of Computer Science and the Centre for Computer Science and Informatics Research. Our research is focused around the interface between software and computer architectures. We are the main contributors for the two programming languages Single Assignment C and S-Net, both of which cater for high-level specifications of concurrent programs.

Single Assignment C is a functional array-programming language with a C like syntax and APL/MATLAB like programming model. The corresponding compiler suite has been in development for 15+ years. Today, it supports auto-parallelisation for a range of architectures, including legacy multi-cores and NVIDIA CUDA. Current research focuses on extending the reach of SAC to novel architectures like the University of Amsterdam’s Microgrid and Intel’s SCC.

S-Net is a language for concurrency engineering. S-Net programs are algebraic formulae that describe the communication pattern of an algorithm on an abstract level. Using our compilation technology, we are able to generate concurrent and distributed implementations from an S-Net specification. Current research in S-Net focuses on adaptivity, real-time support and extending the platform reach.

Across both languages, we are interested in the generalisation of parallel programming principles. As part of the Google summer of code, we contribute generalised high-level vector primitives to the GCC project. We work on abstractions for broad-ranged run-time systems supporting various forms of concurrency. This work applies modern operating systems aspects across various platforms including GPGPUs, FPGAs and embedded systems.

Our work also embodies applications of recent advances in type theory to further enhance expressiveness and to boost run-time efficiency. Ongoing projects include work on a user-specifiable type-system for SAC and a redesign and extension of the S-Net type-system using qualified types and extensible record-types. Furthermore, we are interested in using partial evaluation and abstract interpretation techniques to solve problems that were usually addressed by type systems and SMT solvers.

Adequate spoken and written English skills, as well as command of a functional and an imperative programming language are required. A good bachelor’s degree is mandatory, a master’s degree a plus. Our group is international and we cooperate widely. Good communication skills, an interest to present on international venues as well as the ability to play in a team are essential.

Further details on the available PhD positions can be found at http://www.jobs.ac.uk/job/AAZ241/phd-studentships/

The deadline for applications is the end of May. However, shortlisting will start 19th of May.

Details on the group can be found at the group’s website http://ctca.feis.herts.ac.uk/

Previous and current projects include

http://www.aether-ist.org self-adaptive computing

http://www.apple-core.info multi-core architectures and programming models

http://www.project-advance.eu dynamic adaptation and optimisation

http://www.sac-home.org data-parallel array-programming language

http://www.snet-home.org language for concurrency engineering

Prospective applicants are encouraged to contact Sven-Bodo Scholz

(S.Scholz@herts.ac.uk) to discuss potential research projects before applying

Performance Tools Developer

Cray has an opening for a motivated and skilled software engineer to join its team of performance analysis tools developers. This position includes both significant research and product development activities.

RESPONSIBILITIES:

This work includes the development and implementation of scalable data management techniques; combining analytic and simulation modeling techniques with performance measurements to help users identify problem areas; and helping to bring application optimization knowledge to a wider set of users, as Cray continues to advance the state of the art in performance analysis tools for Cray’s current and future supercomputers.

QUALIFICATIONS:

• M.S. or Ph.D. in Computer Science or similar discipline.
• Three years experience in system software development or equivalent combination of education and experience, particularly with performance tools development.
• Background in high performance computing (HPC) architectures, including multiprocessors, distributed memory systems, and GPU accelerators, with understanding of scientific applications is highly desired.
• Proficiency in C, C++, or Java is required. Working knowledge of Fortran is a plus.
• Background in creating user-interfaces and data visualization is a plus.
• Experience with SQL query optimization is a plus.
• Experience with performance analysis of applications on large-scale systems is a plus.
• Experience in working with large projects, or an advanced thesis in an appropriate area is required.
• Commitment to sound software engineering principles, outstanding problem solving skills, ability to work well in a cooperative development environment, both within and across teams, and good written and verbal communications skills.
• Must be motivated to have an impact on our products, our company, and the state of the art.

OTHER:

The location for this position is in Saint Paul, MN, USA

CONTACT:

Please apply directly at http://www.cray.com/About/Careers/OpportunitiesSearch.aspx or send resume to ldr@cray.com

Compiler Optimization

Cray has an opening for a motivated and skilled software developer to join its Compiler group. The Compiler Optimization Engineer will work on improving the optimization and parallelization phases of the Cray Fortran, C, and C++ compilers. This includes both significant research and product development activities, as Cray continues to advance the state of the art of its compiler across dissimilar architectures. 

RESPONSIBILITIES:

This work includes the design and implementation of new compiler-based optimizations, enhancing existing optimizations, the implementation of new high-level language features, adapting evolving programming models to Cray architectures, and working to improve the overall quality of the compiler.

QUALIFICATIONS:

• B.S. Computer Science, Electrical and Computing Engineering, or similar discipline is required. Advanced degrees are welcome.
• At least 5 years experience in compiler development or equivalent combination of education and experience, particularly with regard to compiler optimization.
• Background in high performance computing (HPC) architectures, including multiprocessors, distributed memory systems, and GPU accelerators, is highly desired.
• Proficiency writing in C is critical, and familiarity with C++ is desired.
• Knowledge of Fortran is a plus.
• Experience in working with large projects, or an advanced thesis in an appropriate area.
• Commitment to sound software engineering principles, outstanding problem solving skills, ability to work well in a cooperative development environment, both within and across teams, and good written and verbal communications skills.
• Must be motivated to have an impact on our products, our company, and the state of the art.

OTHER:

The location for this position is in Saint Paul, MN, USA

CONTACT:

Please apply directly at http://www.cray.com/About/Careers/OpportunitiesSearch.aspx or send resume to ldr@cray.com.

A fully funded position for PhD studies starting in September 2010 is now available in the School of Informatics of the University of Edinburgh. Due to funding restrictions the position is only open to citizens of the European Union.

The PhD will be carried out under the supervision of Prof. Marcelo Cintra (www.homepages.inf.ed.ac.uk/mc) and within the renown CArD group (www.icsa.informatics.ed.ac.uk/compilers). The proposed work is on hardware prefetchers for future many-core systems with high-bandwidth 3D stacked DRAM. For more details on the project please contact Prof. Cintra at mc@staffmail.ed.ac.uk.

Prospective candidates should have completed, or expect to complete by September 2010, a “first-class” (i.e., being ranked at the top 10% of the class) B.Sc. or M.Sc. degree from a well established University. Candidates are expected to have a solid background in one or more of the following: computer architecture, optimizing compilers, parallel programming languages and systems, processor design, and operating systems. Also, programming experience in a major imperative programming language (e.g., C, C++, Java) is desired. Finally, reasonable fluency in English is expected.

Interested candidates should contact Prof. Cintra directly at mc@staffmail.ed.ac.uk providing a C.V. and a letter of reference. The deadline for applications is May 31st 2010.

The University of Edinburgh has been consistently ranked among the top Universities in the world by THES and ARWU. The School of Informatics has been ranked at the very top in the UK by the RAE since this UK government funded assessment began in 1992. The CArD group is one of the leading academic research groups in Europe in the areas of computer architecture, optimizing compilers, and parallel programming.

Associate professor/Senior Lecturer in Embedded Systems and Assistant professor/Research Associate in Embedded Systems

Uppsala University has recently been awarded several grants for long-term research efforts in areas ranging from multicore programming, embedded systems to sensor networks and is expanding in several directions. The open positions are intended to strengthen and complement the existing expertise in embedded and real-time systems.

The successful candidate for associate professor may be promoted to full professor directly if she/he is jugded to be sufficiently competent.

The appointment for assisstant professor offers an ideal career opportunity for young scholars, which includes about 75 percent time for research for four years.

The positions provide excellent opportunities for interaction with existing research efforts at the department, including, e.g., multicore computing, embedded systems, computer networks, formal specification and verification, and high-performance computing. More information is available at http://www.it.uu.se/research/.

Application Deadline: April 12. Women are especially encouraged to apply. More information on the application procedure can be found at http://www.personalavd.uu.se/ledigaplatser/625unlekt_eng.html

and http://www.personalavd.uu.se/ledigaplatser/624forass_eng.html

Eindhoven University of Technology

Faculty of Electrical Engineering

Eindhoven

The Netherlands

FTE 1.0

Application Deadline: 31-03-2010

Vacancy Number: V36.1075

The Faculty of Electrical Engineering delivers education and performs scientific and technological research in the broad discipline of Electrical Engineering. Electrical Engineering covers the application of electrical phenomena with respect to energy, information processing and telecommunication, as well as, electrical and electronic components, and the technology involved. Both hardware, in the form of electronic circuits and accessories, and software, in the form of system software for electro-technical applications, are the subject of study. Existing or new electrical devices, components and systems are analyzed, designed, implemented, controlled and realized. In addition, the maintenance of these systems is the subject of research, as is the societal relevance of electrical engineering and information technology.

Position

The position is in the Section of Digital Circuits and Formal Design Methods (DCFDM) of the Electronic Systems (ES) Group. The mission of the ES Group is to provide a scientific basis for design trajectories of digital electronic circuits and systems ‘from (generalized) algorithm to realization’. To identify the key problems, and verify the validity, robustness and completeness of our results, we develop, implement and maintain consistent and complete flows, and use them for realizing innovative hardware, with emphasis on video processing and embedded architectures. The mission of the DCFDM Section is research and development of theory, methods and EDA tools for modeling, analysis, synthesis and optimization of digital circuits and systems to adequately cope with the increasing complexity and challenges of the nano-electronic technologies. It has an internationally recognized expertise in design theory, methodology and electronic design automation for embedded system design and hardware synthesis. It has also experience with FPGA-based design, (re-)configurable architectures, multi-objective circuit and system optimization and automatic architecture synthesis for (heterogeneous) platform-based systems.

Project

The research work will be performed in the scope of the Architecture Synthesis and Application Mapping (ASAM) project, being a part of the European research program ARTEMIS. The ASAM project addresses the problem of an automatic coherent architecture synthesis and application mapping for heterogeneous multi-processor embedded systems based on configurable application-specific instruction-set processors (ASIPs). It aims at defining a new unified design methodology, as well as, related synthesis and prototyping tool-chains for: multi-objective design space exploration for configurable heterogeneous multi-ASIP systems and identification of the application-tailored system architectures; automatic architecture instantiation or customization of particular application-tailored processors, memories and communication structures of the system architecture; optimal hardware synthesis of the created platform; automatic application mapping on the resulting multi-processor heterogeneous platform; and software compiler retargeting and automatic software compilation, all when accounting for the platform hardware characteristics and for the functional and extra-functional requirements and trade-offs.

The research work will be focused on the automatic architecture instantiation or customization of the application-tailored ASIPs, including their extension with new application-specific instructions and related hardware, optimal synthesis of the ASIPs’ hardware, and collaboration of these micro-architecture and hardware synthesis tasks with the memory and communication architecture synthesis, as well as, with the macro-architecture synthesis of the whole heterogeneous multi-processor system.

Tasks

The main tasks include:

• research work in the scope of the above described project involving development of new design methods, and related electronic design automation (EDA) analysis and synthesis flows and tools, software implementation of the prototype EDA tools and flows, and experimental research with their use;
• assistance to the project coordinator in implementation of the coordination decisions, as well as, coordination, organization, communication and reporting activities, and in supervision of the junior researchers and students;
• establishing and adequately running of the project web-page.

Requirements

Candidates for this Post-doc researcher position should meet the following requirements:

• MSc in Embedded Systems, Computer Engineering, Electronics, Electrical Engineering, Information Technology or related area, with an advanced knowledge or minor/majors in subjects related to electronic design automation, (embedded) processor architectures and/or SoC design;
• Ph.D. degree preferably or P.D. Eng. Degree and an equivalent amount of experience, or MSc degree and a proven large amount of experience and substantial achievements in research and development related to electronic design automation, (embedded) processor architectures and/or SoC design;
• a solid knowledge of and substantial experience in software design and programming, including knowledge of and experience with programming in C++ and/or C;
• excellent invention and learning abilities;
• excellent analytical, organizational and communication skills, including an ability of effective and efficient individual work, as well as, easy cooperation in a team with supervisors, students, other researchers and companies, and excellent English language capabilities both in writing and speaking;
• a substantial knowledge of or experience with ASIP processors, instruction-set synthesis, (re-)configurable systems, FPGA-based design and prototyping, and related EDA tools will be a premium.

Appointment and Salary

The appointment is of immediately and can start as soon as possible. The appointment will be for three years. The gross monthly salary will be in accordance with the Collective Labor agreement of the Dutch Universities (CAO NU) and amounts to at least € 2861 per month (initially, scale 10.4) depending on prior experience. An offer will be based on your knowledge and experience. An attractive package of fringe benefits (including excellent work facilities, end of the year allowance and sport facilities). Moreover an 8% bonus share (holiday supplement) is provided annually.

Information

For more information on the project, tasks or requirements please contact Dr. ir. L. Józwiak, tel. +31-(0)40-2473645, e-mail: L.Jozwiak@tue.nl.

For terms on employment please contact: Mr. P.F.M. Tiel Groenestege, HR advisor of the Faculty of Electrical Engineering tel. +31-(0)40-2472004, e-mail: p.f.m.tiel.groenestege@tue.nl .

More information and on-line application form can be found on the TU/e web-pages:

http://jobs.tue.nl/wd/plsql/wd_portal.search_results?p_web_site_id=3085&p_category_id=3713&p_show_results=Y&p_form_type=CHECKBOX&p_no_days=999&p1=6047&p1_val=Any&p2=6048&p2_val=Department+of+Electrical+Engineering&p_text=&p_save_search=N

and

http://w3.tue.nl/en/services/dpo/excellent_jobs_for_excellent_people

Visiting Research Programmer

Department of Computer Science

University of Illinois Urbana-Champaign

The Universal Parallel Computing Research Center (UPCRC) at the University of Illinois (http://www.upcrc.illinois.edu/) is seeking a full-time Visiting Research Programmer to work on the Deterministic Parallel C++ project.  UPCRC Illinois is a world-class research center that aims to make parallel programming far easier than it is today.  The programmer will assist the DPJ group with programming tasks that arise in their research, such as developing, distributing and supporting the DPC++ programming language implementation.  These tasks will include DPC++ language implementation and optimization, GUI programming, application parallelization and tuning, documentation, open source software release and support, Web site and Wiki maintenance, etc.  The Visiting Research Programmer will have the opportunity to work in close collaboration with UPCRC researchers on sophisticated new concepts in parallel programming languages, compilers and applications, and to assist the group in deploying the technology to external users.

Required qualifications for this position include:

- Master’s degree in Computer Science or related field (Bachelor’s degree with 3 years or more of strong programming skills will be considered as well)

- Strong C++ programming experience

- Strong, recent experience with a large, modern compiler

- Strong experience with programming and using Linux/Unix platforms

- Experience with shared memory parallel programming

- Demonstrated ability to work well with a team

- Demonstrated initiative and ability to work independently

- Good communication and writing skills

Preferred qualifications for this position include:

      -     PhD in Computer Science or related field

- Research or advanced development in compiler optimizations

- Research or advanced development in parallel application programming

- Experience with Visual C++ on Windows

This position will be available as soon as possible after the closing date and is a 12-month, temporary, full-time academic professional appointment with the possibility of becoming permanent at a future date.  Salary is commensurate with education and experience.  Applicants may be interviewed before the closing date, but no hiring decision will be made until after that date.

To apply for this position, please create your candidate profile at https://jobs.illinois.edu and upload your cover letter, resume, and names/contact information for three references by 04/02/2010.  For recent graduates, at least two of the references must be able to describe your previous programming work experience.  All requested information must be submitted for your application to be considered.  For further information regarding application procedures, contact Kathy Buss at 217-333-6804 or kbuss@illinois.edu.

The University of Illinois is an Affirmative Action/Equal Opportunity Employer.  The administration, faculty, and staff embrace diversity and are committed to attracting qualified candidates who also embrace and value diversity and inclusivity.

Eindhoven University of Technology

Faculty of Electrical Engineering

Eindhoven

The Netherlands

FTE 1.0

Application Deadline: 31-03-2010

Vacancy Number: V36.1076

The Faculty of Electrical Engineering concerns the research and education of the Electrical Engineering discipline. Electrical Engineering covers the application of electrical phenomena with respect to energy transfer, telecommunication, as well as calculation and processing of information, and the technology involved. Both hardware, in the form of electronic circuits and accessories, and software, in the form of system software for electro-technical applications, are the subject of study. Existing and new electrical components and systems are analyzed, designed and realized. In addition, the maintenance of these systems is the subject of research, as is the relevance of electrical engineering and informatics for society.

Position

The position is in the Section of Digital Circuits and Formal Design Methods (DCFDM) of the Electronic Systems (ES) Group. The mission of the ES Group is to provide a scientific basis for design trajectories of digital electronic circuits and systems ‘from (generalized) algorithm to realization’. To identify the key problems, and verify the validity, robustness and completeness of our results, we develop, implement and maintain consistent and complete flows, and use them for realizing innovative hardware with emphasis on video processing and embedded architectures. The mission of the DCFDM Section is research and development of theory, methods and EDA tools for modeling, analysis, synthesis and optimization of digital circuits and systems to adequately cope with the increasing complexity and challenges of the nano-electronic technologies. It has an internationally recognized expertise in design theory, methodology and electronic design automation for embedded system design and hardware synthesis. It has also experience with FPGA-based design, (re-)configurable architectures, multi-objective circuit and system optimization and automatic architecture synthesis for (heterogeneous) platform-based systems.

Project

The research work will be performed in the scope of the Architecture Synthesis and Application Mapping (ASAM) project, being a part of the European research program ARTEMIS. The ASAM project addresses the problem of an automatic coherent architecture synthesis and application mapping for heterogeneous multi-processor embedded systems based on configurable application-specific instruction-set processors (ASIPs). It aims at defining a new unified design methodology, as well as, related synthesis and prototyping tool-chains for: multi-objective design space exploration for configurable heterogeneous multi-ASIP systems and identification of the application-tailored system architecture; automatic architecture instantiation or customization of particular application-tailored processors, memories and communication structures of the system architecture; optimal hardware synthesis of the created platform; automatic application mapping on the resulting multi-processor heterogeneous platform; and software compiler retargeting and automatic software compilation, all when accounting for the platform hardware characteristics and for the functional and extra-functional requirements and trade-offs.

The research work will be focused on the automatic architecture instantiation or customization of the application-tailored ASIPs, including their extension with new application-specific instructions and related hardware, optimal synthesis of the ASIPs’ hardware, and collaboration of these micro-architecture and hardware synthesis tasks with the memory and communication architecture synthesis, as well as, with the macro-architecture synthesis of the whole heterogeneous multi-processor system.

Tasks

The research work in the scope of the above described project involving development of new design methods, and related electronic design automation (EDA) analysis and synthesis flows and tools, software implementation of the prototype EDA tools and flows, and experimental research with their use.

Requirements

Candidates for this PhD position should meet the following requirements:

• MSc in Embedded Systems, Computer Engineering, Electronics, Electrical Engineering, Information Technology or related area, with an advanced knowledge or minor/majors in subjects related to electronic design automation, (embedded) processor architectures and/or SoC design;
• a solid knowledge of and substantial experience in software design and programming, including knowledge of and experience with programming in C++ and/or C;
• excellent invention and learning abilities;
• excellent analytical, organizational and communication skills, including an ability of effective and efficient individual work, as well as, easy cooperation in a team with supervisors, students, other researchers and companies, and excellent English language capabilities both in writing and speaking;
• a substantial knowledge of or experience with ASIP processors, instruction-set synthesis, (re-)configurable systems, FPGA-based design and prototyping, and related EDA tools will be a premium.

Appointment and Salary

The appointment is for four years. The research in this project must be concluded with writing a PhD thesis. A salary is offered starting at EUR 2042 per month (gross) in the first year and increasing up to EUR 2612 per month (gross) in the last year. Moreover 8% bonus share (holiday supplement) is provided annually. Assistance for finding accommodation can be given. The university offers an attractive package of fringe benefits such as excellent technical infrastructure, child care, savings schemes, and excellent sports facilities.
TU/e offers you also the opportunity for personal development by developing your social and communication skills. We do this by offering every PhD student a series of courses that are part of the Proof program as an excellent addition to your scientific education (Proof program).

Information

For more information on the project, tasks or requirements please contact Dr. ir. L. Józwiak, tel. +31-(0)40-2473645, e-mail: L.Jozwiak@tue.nl.
For terms on employment please contact: Mr. P.F.M. Tiel Groenestege, HR advisor of the Faculty of Electrical Engineering tel. +31-(0)40-2472004, e-mail: p.f.m.tiel.groenestege@tue.nl .

More information and on-line application form can be found on the TU/e web-pages:

http://jobs.tue.nl/wd/plsql/wd_portal.search_results?p_web_site_id=3085&p_category_id=3713&p_show_results=Y&p_form_type=CHECKBOX&p_no_days=999&p1=6047&p1_val=Any&p2=6048&p2_val=Department+of+Electrical+Engineering&p_text=&p_save_search=N

and

http://w3.tue.nl/en/services/dpo/excellent_jobs_for_excellent_people